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Uos cs limit from dm #1689

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merged 3 commits into from
Nov 1, 2018
Merged

Uos cs limit from dm #1689

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e347b0e
DM: set cs_limit from DM side for UOS
fyin1 Oct 29, 2018
84c942f
HV: save the cs limit field for SOS
fyin1 Oct 29, 2018
794157c
hv: avoid hardcode cs.limit in set_vcpu_regs()
fyin1 Oct 29, 2018
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1 change: 1 addition & 0 deletions devicemodel/core/sw_load_bzimage.c
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Original file line number Diff line number Diff line change
Expand Up @@ -344,6 +344,7 @@ acrn_sw_load_bzimage(struct vmctx *ctx)

ctx->bsp_regs.vcpu_regs.cs_sel = 0x10U;
ctx->bsp_regs.vcpu_regs.cs_ar = 0xC09BU;
ctx->bsp_regs.vcpu_regs.cs_limit = 0xFFFFFFFFU;

ctx->bsp_regs.vcpu_regs.ds_sel = 0x18U;
ctx->bsp_regs.vcpu_regs.ss_sel = 0x18U;
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1 change: 1 addition & 0 deletions devicemodel/core/sw_load_elf.c
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Expand Up @@ -283,6 +283,7 @@ acrn_sw_load_elf(struct vmctx *ctx)

ctx->bsp_regs.vcpu_regs.cs_ar = 0xCF9BU;
ctx->bsp_regs.vcpu_regs.cs_sel = 0x8U;
ctx->bsp_regs.vcpu_regs.cs_limit = 0xFFFFFFFFU;

ctx->bsp_regs.vcpu_regs.ds_sel = 0x10U;
ctx->bsp_regs.vcpu_regs.ss_sel = 0x10U;
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1 change: 1 addition & 0 deletions devicemodel/core/sw_load_vsbl.c
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Expand Up @@ -307,6 +307,7 @@ acrn_sw_load_vsbl(struct vmctx *ctx)
ctx->bsp_regs.vcpu_regs.cr0 = 0x30U;
ctx->bsp_regs.vcpu_regs.cs_ar = 0x009FU;
ctx->bsp_regs.vcpu_regs.cs_sel = 0xF000U;
ctx->bsp_regs.vcpu_regs.cs_limit = 0xFFFFU;
ctx->bsp_regs.vcpu_regs.cs_base = (VSBL_TOP(ctx) - 16) &0xFFFF0000UL;
ctx->bsp_regs.vcpu_regs.rip = (VSBL_TOP(ctx) - 16) & 0xFFFFUL;
ctx->bsp_regs.vcpu_regs.gprs.rsi = CONFIGPAGE_OFF(ctx);
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3 changes: 2 additions & 1 deletion devicemodel/include/public/acrn_common.h
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Expand Up @@ -309,7 +309,8 @@ struct acrn_vcpu_regs {
uint64_t reserved_64[4];

uint32_t cs_ar;
uint32_t reserved_32[4];
uint32_t cs_limit;
uint32_t reserved_32[3];

/* don't change the order of following sel */
uint16_t cs_sel;
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14 changes: 14 additions & 0 deletions hypervisor/arch/x86/cpu_save_boot_ctx.S
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Expand Up @@ -32,6 +32,13 @@ cpu_primary_save_32:
/* Clear Limit field, bit 8-11 */
andl $0x0000f0ff, %ecx
mov %ecx, BOOT_CTX_CS_AR_OFFSET(%eax)

/* Save CS limit field */
mov %cs, %cx
xor %edx, %edx
lsl %ecx, %edx
mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%eax)

mov %es, BOOT_CTX_ES_SEL_OFFSET(%eax)
mov %ss, BOOT_CTX_SS_SEL_OFFSET(%eax)
mov %ds, BOOT_CTX_DS_SEL_OFFSET(%eax)
Expand Down Expand Up @@ -62,6 +69,13 @@ cpu_primary_save_64:
/* Clear Limit field, bit 8-11 */
andl $0x0000f0ff, %ecx
mov %ecx, BOOT_CTX_CS_AR_OFFSET(%r8)

/* Save CS limit field */
mov %cs, %cx
xor %edx, %edx
lsl %ecx, %edx
mov %edx, BOOT_CTX_CS_LIMIT_OFFSET(%r8)

mov %es, BOOT_CTX_ES_SEL_OFFSET(%r8)
mov %ss, BOOT_CTX_SS_SEL_OFFSET(%r8)
mov %ds, BOOT_CTX_DS_SEL_OFFSET(%r8)
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17 changes: 10 additions & 7 deletions hypervisor/arch/x86/guest/vcpu.c
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Expand Up @@ -189,16 +189,17 @@ void set_vcpu_regs(struct vcpu *vcpu, struct acrn_vcpu_regs *vcpu_regs)
ectx = &(vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].ext_ctx);
ctx = &(vcpu->arch_vcpu.contexts[vcpu->arch_vcpu.cur_context].run_ctx);

if (vcpu_regs->cs_ar & (1U << 15U)) {
limit = 0xFFFFFFFFU;
} else {
limit = 0xFFFFU;
}

/* NOTE:
* This is to set the attr and limit to default value.
* If the set_vcpu_regs is used not only for vcpu state
* initialization, this part of code needs be revised.
*/
if (vcpu_regs->cr0 & CR0_PE) {
attr = PROTECTED_MODE_DATA_SEG_AR;
limit = PROTECTED_MODE_SEG_LIMIT;
} else {
attr = REAL_MODE_DATA_SEG_AR;
limit = REAL_MODE_SEG_LIMIT;
}

for (seg = &(ectx->cs); seg <= &(ectx->gs); seg++) {
Expand All @@ -209,9 +210,10 @@ void set_vcpu_regs(struct vcpu *vcpu, struct acrn_vcpu_regs *vcpu_regs)
sel++;
}

/* override cs attr/base */
/* override cs attr/base/limit */
ectx->cs.attr = vcpu_regs->cs_ar;
ectx->cs.base = vcpu_regs->cs_base;
ectx->cs.limit = vcpu_regs->cs_limit;

ectx->gdtr.base = vcpu_regs->gdt.base;
ectx->gdtr.limit = vcpu_regs->gdt.limit;
Expand Down Expand Up @@ -271,6 +273,7 @@ static struct acrn_vcpu_regs realmode_init_regs = {
.cs_ar = REAL_MODE_CODE_SEG_AR,
.cs_sel = REAL_MODE_BSP_INIT_CODE_SEL,
.cs_base = 0xFFFF0000UL,
.cs_limit = 0xFFFFU,
.rip = 0xFFF0UL,
.cr0 = CR0_ET | CR0_NE,
.cr3 = 0UL,
Expand Down
2 changes: 2 additions & 0 deletions hypervisor/include/arch/x86/guest/guest.h
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Expand Up @@ -69,6 +69,8 @@
#define REAL_MODE_CODE_SEG_AR (0x009fU)
#define PROTECTED_MODE_DATA_SEG_AR (0xc093U)
#define PROTECTED_MODE_CODE_SEG_AR (0xc09bU)
#define REAL_MODE_SEG_LIMIT (0xffffU)
#define PROTECTED_MODE_SEG_LIMIT (0xffffffffU)
#define DR7_INIT_VALUE (0x400UL)
#define LDTR_AR (0x0082U) /* LDT, type must be 2, refer to SDM Vol3 26.3.1.2 */
#define TR_AR (0x008bU) /* TSS (busy), refer to SDM Vol3 26.3.1.2 */
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2 changes: 2 additions & 0 deletions hypervisor/include/arch/x86/guest/vm0_boot.h
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Expand Up @@ -22,6 +22,7 @@
#define BOOT_CTX_FS_SEL_OFFSET 276
#define BOOT_CTX_GS_SEL_OFFSET 278
#define BOOT_CTX_CS_AR_OFFSET 248
#define BOOT_CTX_CS_LIMIT_OFFSET 252
#define BOOT_CTX_EFER_LOW_OFFSET 200
#define BOOT_CTX_EFER_HIGH_OFFSET 204
#define SIZE_OF_BOOT_CTX 296
Expand All @@ -40,6 +41,7 @@
#define BOOT_CTX_FS_SEL_OFFSET 276U
#define BOOT_CTX_GS_SEL_OFFSET 278U
#define BOOT_CTX_CS_AR_OFFSET 248U
#define BOOT_CTX_CS_LIMIT_OFFSET 252U
#define BOOT_CTX_EFER_LOW_OFFSET 200U
#define BOOT_CTX_EFER_HIGH_OFFSET 204U
#define SIZE_OF_BOOT_CTX 296U
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3 changes: 2 additions & 1 deletion hypervisor/include/public/acrn_common.h
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Expand Up @@ -295,7 +295,8 @@ struct acrn_vcpu_regs {
uint64_t reserved_64[4];

uint32_t cs_ar;
uint32_t reserved_32[4];
uint32_t cs_limit;
uint32_t reserved_32[3];

/* don't change the order of following sel */
uint16_t cs_sel;
Expand Down