Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

armstub8.S sets RES0 bits in cptr_el3 #95

Open
asurati opened this issue Mar 26, 2019 · 0 comments
Open

armstub8.S sets RES0 bits in cptr_el3 #95

asurati opened this issue Mar 26, 2019 · 0 comments

Comments

@asurati
Copy link

asurati commented Mar 26, 2019

It moves 0x33ff into cptr_el3.

Cortex A53 TRM lists all bits except 10,20 and 31 as RES0.
Luckily, 0x33ff is a value where those 3 bits are 0 (and the 12 ON bits in the value are RES0 in the register), thus resulting in disabling of fp/simd traps to el3, as expected. Storing a zero into, or read-modify-write of, cptr_el3, would be proper.

The number 0x33ff fits more appropriately into cptr_el2, given the intention of disabling fp/simd traps to el2.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant