Update tests

tests/verilog-conversion/conftest.py

@@ -25,7 +25,7 @@ def exdriver(request):
 def pytest_addoption(parser):
     """add options for controlling the running of tests"""
     # whether output the clang output
-    parser.addoption("--tool-output", action="store_true")
+    parser.addoption("--tool-output", action="store_true", default=False)
 
 
 def pytest_generate_tests(metafunc):

tests/verilog-conversion/driver.py

@@ -120,7 +120,6 @@ def generate_sexp(self, path, output_folder, keep_sexp=False, verbose=False):
             print('sexp_loc: ', sexp_loc)
             print('sexp_filename: ', sexp_filename)
             print('output_filename: ', output_filename)
-        ok = True
         try:
             if verbose:
                 print('cmd: ', ' '.join(cmdline))
@@ -131,12 +130,13 @@ def generate_sexp(self, path, output_folder, keep_sexp=False, verbose=False):
                             stdout=null, 
                             stderr=null)
             move_required = os.path.normpath(sexp_loc) != os.path.normpath(output_filename)
-            if os.path.isfile(output_filename):
+            if os.path.isfile(sexp_loc):
                 if move_required:
                     move(sexp_loc, output_folder)
                 # subprocess.run('mv {} {}'.format(sexp_loc, output_folder), shell=True)
                 return True, output_filename
             else:
+                print("Failed Path 1")
                 return False, None
         except:
             raise
@@ -148,7 +148,7 @@ def generate_sexp(self, path, output_folder, keep_sexp=False, verbose=False):
             if keep_sexp and os.path.normpath(sexp_loc) != os.path.normpath(output_filename):
                 subprocess.run('rm -f {}'.format(sexp_loc), shell=True)
 
-        return ok, output_filename
+        return False, None
 
     """
     Takes .cpp as input, generate .v

tests/verilog-conversion/test_sreg.py

@@ -2,14 +2,18 @@
 from util.sexpdiff import sexpdiff
 from util.vparser import VerilogParser
 from shutil import copy
+import os
 
 
 def test_sreg_sexp(tmpdir, llnldriver, tool_output):
     conf = llnldriver.conf
     filename = conf.get_module_name('sreg.cpp')
     output_folder = tmpdir
+    copy(filename, output_folder)
+    cpp_path = str(output_folder) + '/' + 'sreg.cpp'
+    assert os.path.isfile(cpp_path)
     res, filename = llnldriver.generate_sexp(
-        path=filename,
+        path=cpp_path,
         output_folder=output_folder,
         verbose=tool_output,
         keep_sexp=True
@@ -41,6 +45,7 @@ def test_sreg_verilog(tmpdir, llnldriver, tool_output):
     print(str(diff_info))
     assert diff_info is None, 'should be no diff in Verilog'
 
+
 def test_sreg_sexp_to_verilog(tmpdir, llnldriver, tool_output):
     conf = llnldriver.conf
     filename = conf.get_golden_sexp_name('sreg_hdl.txt')