add vcgez, vcgtz, vclez, vcltz neon instructions

[SparrowLii]

All are automatically generated single-parameter comparison instructions. In order to be consistent with the implementation in Clang, some changes have been made to stdarch-gen.

[rust-highfive]

r? @Amanieu

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[Amanieu]

Why not just use simd_ge here?

[SparrowLii]

This is to be consistent with Clang's implementation. The following is the test I did in https://godbolt.org/:

#include <arm_neon.h>
int test() {
  return (int) vcgez_s32;
}        

And the Output:

define dso_local i32 @test() local_unnamed_addr #0 {
    ret i32 ptrtoint (<2 x i32> (<2 x i32>)* @vcgez_s32 to i32)
}

define internal <2 x i32> @vcgez_s32(<2 x i32> %0) #1 {
    %2 = ashr <2 x i32> %0, <i32 31, i32 31>
    %3 = xor <2 x i32> %2, <i32 -1, i32 -1>
    ret <2 x i32> %3
}

attributes #0 = { norecurse nounwind readnone uwtable willreturn "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" }
attributes #1 = { alwaysinline norecurse nounwind readnone uwtable willreturn "frame-pointer"="non-leaf" "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" }

[Amanieu]

If you compile with -O0 you will see that Clang actually emits an icmp sge. LLVM optimizations are then turning this into a shift + xor.

[SparrowLii]

The url of godbolt is from here: #148

[Amanieu]

That usually works, but in this particular case it gives a different result because the IR is not the one generated by Clang directly: it is the IR after LLVM has run optimization passes that expand the icmp eq into shift and xor.

You can use simd_ge in Rust and it will produce the same IR as Clang.

[SparrowLii]

Umm.. That's right. If we use an implementation consistent with -O0, can we ensure that LLVM achieves the same optimization? If so, we should indeed use simd_ge IMO

[Edit] OK, got it

[Amanieu]

We run the same LLVM passes as Clang (mostly) so rustc will also transform simd_ge into a shift + xor.

[SparrowLii]

Thanks for explanation!

[Amanieu]

And simd_lt here?

[SparrowLii]

Same as above, the following is my test in https://godbolt.org/:

#include <arm_neon.h>
int test() {
return (int) vcltz_s32;
}                                     

And the Output:

define dso_local i32 @test() local_unnamed_addr #0 {
    ret i32 ptrtoint (<2 x i32> (<2 x i32>)* @vcltz_s32 to i32)
}

define internal <2 x i32> @vcltz_s32(<2 x i32> %0) #1 {
    %2 = ashr <2 x i32> %0, <i32 31, i32 31>
    ret <2 x i32> %2
}

attributes #0 = { norecurse nounwind readnone uwtable willreturn "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" }
attributes #1 = { alwaysinline norecurse nounwind readnone uwtable willreturn "frame-pointer"="non-leaf" "min-legal-vector-width"="64" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" }

[Amanieu]

Can you add ARM versions of these functions?

[SparrowLii]

Can you add ARM versions of these functions?

It seems that these instructions are unique to aarch64 and only accept signed parameters. I can't compile the version of arm on godbolt either.
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vcltz

[Amanieu]

You are right.