[Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 #19681

ayurkiv-nvda · 2024-07-25T09:42:34Z

Why I did it

A new SKUs for MSN4700 Platform: Mellanox-SN4700-O32 and Mellanox-SN4700-V64

Requirements for Mellanox-SN4700-O32:

8 x 400Gbps uplink to T2 switch (O13 to O20)
24 x 400Gbps downlinks to T0 switch (O1-O12, O21-O32)
Breakout mode No breakout mode. All ports working in 400Gb mode. .
FEC mode: RS
Type of transceiver: 400Gb Optical.
warm boot should be supported “No for T1 role”
VxLAN source port range set N/A
Static Policy Based Hashing supported N/A
Cable length “T0-T1 40m default, 300m max; T1-T2 2000m”
Tradition buffer model is must “Yes”
Shared headroom should be supported “Yes”
Over-subscription ratio: “2”.

Requirements for Mellanox-SN4700-V64

16 x 200Gbps uplink to T1 switch (V-25&V26 to V-39&40)
48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64)
Breakout mode split from 400Gbps ports (2x200)
FEC mode: RS
Type of transceiver: 200Gb AOC between T0 and T1; 200Gb DAC between T0 and host.
warm boot should be supported “Yes for T0 role”
VxLAN source port range set N/A
Static Policy Based Hashing supported N/A
Cable length “T0-T1 40m default, 300m max, T0-Server 5m”
Tradition buffer model is must “Yes”
Shared headroom should be supported “Yes”
Over-subscription ratio: “2”.

Additional Details:

QoS configs for Mellanox-SN4700-V64 updated in order to fulfill Dual-ToR buffer (+DSCP remapping) requirements
Support for independent module added for both SKUs, so Auto-negotiation changed to NO

Work item tracking

Microsoft ADO (number only):

How I did it

How to verify it

Run full regression

Which release branch to backport (provide reason below if selected)

Tested branch (Please provide the tested image version)

Description for the changelog

Link to config_db schema for YANG module changes

A picture of a cute animal (not mandatory but encouraged)

ayurkiv-nvda · 2024-07-25T09:55:04Z

Related PR (for master):
sonic-net/sonic-utilities#3450

ayurkiv-nvda · 2024-07-25T09:59:32Z

Related PR (for 202311 )
sonic-net/sonic-utilities#3438

ayurkiv-nvda · 2024-07-25T10:34:54Z

Related PR (for 202405 )
sonic-net/sonic-utilities#3451

DavidZagury · 2024-07-25T17:32:14Z

device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-V64/port_config.ini

+## See the License for the specific language governing permissions and
+## limitations under the License.
+##
+# name          lanes         


The title headers are not complete.
Also should probably add the autoneg/subport here too?
Although this file was replaced by the hwsku.json file

headers updated
autoneg and subport specified in hwsku file, correct

device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-V64/port_config.ini

stephenxs · 2024-07-26T08:54:46Z

48 x 400Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64) => 48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64)?

device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/pg_profile_lookup.ini

ayurkiv-nvda · 2024-07-26T17:14:42Z

48 x 400Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64) => 48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64)?

Updated

stephenxs

buffer/QoS part LGTM

Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

…O32 and Mellanox-SN4700-V64 Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

…SN4700-V64 SKUs Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

…-link pg_profile_lookup.ini file Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

bingwang-ms · 2024-07-29T16:58:59Z

@liushilongbuaa Can you please suggest how can we fix the ms_checker failure? I retriggered it, but seems that didn't help.

bingwang-ms · 2024-07-29T17:07:14Z

@prgeor Can you help double-check on the AN and independent mode configuration?

device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O32/hwsku.json

dprital

SubPort config should be added to hwsku.json

bingwang-ms · 2024-08-05T16:36:14Z

@ayurkiv-nvda Please check and address the comments from @dprital .

dprital · 2024-08-05T16:42:41Z

@ayurkiv-nvda Please check and address the comments from @dprital .

@bingwang-ms , as there are no splits in this SKU, SubPort is not required. so it is OK from my POV, and I approved the PR as well. Thnaks.

…nic-net#19681) A new SKUs for MSN4700 Platform: Mellanox-SN4700-O32 and Mellanox-SN4700-V64 Requirements for Mellanox-SN4700-O32: 8 x 400Gbps uplink to T2 switch (O13 to O20) 24 x 400Gbps downlinks to T0 switch (O1-O12, O21-O32) Breakout mode No breakout mode. All ports working in 400Gb mode. . FEC mode: RS Type of transceiver: 400Gb Optical. warm boot should be supported “No for T1 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max; T1-T2 2000m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Requirements for Mellanox-SN4700-V64 16 x 200Gbps uplink to T1 switch (V-25&V26 to V-39&40) 48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64) Breakout mode split from 400Gbps ports (2x200) FEC mode: RS Type of transceiver: 200Gb AOC between T0 and T1; 200Gb DAC between T0 and host. warm boot should be supported “Yes for T0 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max, T0-Server 5m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Additional Details: QoS configs for Mellanox-SN4700-V64 updated in order to fulfill Dual-ToR buffer (+DSCP remapping) requirements Support for independent module added for both SKUs, so Auto-negotiation changed to NO Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

mssonicbld · 2024-08-05T16:56:56Z

Cherry-pick PR to 202311: #19822

mssonicbld · 2024-08-05T16:57:11Z

Cherry-pick PR to 202405: #19823

…9681) A new SKUs for MSN4700 Platform: Mellanox-SN4700-O32 and Mellanox-SN4700-V64 Requirements for Mellanox-SN4700-O32: 8 x 400Gbps uplink to T2 switch (O13 to O20) 24 x 400Gbps downlinks to T0 switch (O1-O12, O21-O32) Breakout mode No breakout mode. All ports working in 400Gb mode. . FEC mode: RS Type of transceiver: 400Gb Optical. warm boot should be supported “No for T1 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max; T1-T2 2000m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Requirements for Mellanox-SN4700-V64 16 x 200Gbps uplink to T1 switch (V-25&V26 to V-39&40) 48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64) Breakout mode split from 400Gbps ports (2x200) FEC mode: RS Type of transceiver: 200Gb AOC between T0 and T1; 200Gb DAC between T0 and host. warm boot should be supported “Yes for T0 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max, T0-Server 5m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Additional Details: QoS configs for Mellanox-SN4700-V64 updated in order to fulfill Dual-ToR buffer (+DSCP remapping) requirements Support for independent module added for both SKUs, so Auto-negotiation changed to NO Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

…nic-net#19681) A new SKUs for MSN4700 Platform: Mellanox-SN4700-O32 and Mellanox-SN4700-V64 Requirements for Mellanox-SN4700-O32: 8 x 400Gbps uplink to T2 switch (O13 to O20) 24 x 400Gbps downlinks to T0 switch (O1-O12, O21-O32) Breakout mode No breakout mode. All ports working in 400Gb mode. . FEC mode: RS Type of transceiver: 400Gb Optical. warm boot should be supported “No for T1 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max; T1-T2 2000m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Requirements for Mellanox-SN4700-V64 16 x 200Gbps uplink to T1 switch (V-25&V26 to V-39&40) 48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64) Breakout mode split from 400Gbps ports (2x200) FEC mode: RS Type of transceiver: 200Gb AOC between T0 and T1; 200Gb DAC between T0 and host. warm boot should be supported “Yes for T0 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max, T0-Server 5m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Additional Details: QoS configs for Mellanox-SN4700-V64 updated in order to fulfill Dual-ToR buffer (+DSCP remapping) requirements Support for independent module added for both SKUs, so Auto-negotiation changed to NO Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

…-V64 (#20002) * [Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 (#19681) A new SKUs for MSN4700 Platform: Mellanox-SN4700-O32 and Mellanox-SN4700-V64 Requirements for Mellanox-SN4700-O32: 8 x 400Gbps uplink to T2 switch (O13 to O20) 24 x 400Gbps downlinks to T0 switch (O1-O12, O21-O32) Breakout mode No breakout mode. All ports working in 400Gb mode. . FEC mode: RS Type of transceiver: 400Gb Optical. warm boot should be supported “No for T1 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max; T1-T2 2000m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Requirements for Mellanox-SN4700-V64 16 x 200Gbps uplink to T1 switch (V-25&V26 to V-39&40) 48 x 200Gbps downlinks to servers (Left panel downlink ports: V-1&2 to V-23&24; Right panel downlink ports: V-41&42 to V-63&64) Breakout mode split from 400Gbps ports (2x200) FEC mode: RS Type of transceiver: 200Gb AOC between T0 and T1; 200Gb DAC between T0 and host. warm boot should be supported “Yes for T0 role” VxLAN source port range set N/A Static Policy Based Hashing supported N/A Cable length “T0-T1 40m default, 300m max, T0-Server 5m” Tradition buffer model is must “Yes” Shared headroom should be supported “Yes” Over-subscription ratio: “2”. Additional Details: QoS configs for Mellanox-SN4700-V64 updated in order to fulfill Dual-ToR buffer (+DSCP remapping) requirements Support for independent module added for both SKUs, so Auto-negotiation changed to NO Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com> * [Mellanox][202311] Use pg_profile_lookup.ini from SN4280 for Mellanox-SN4700-O32 and Mellanox-SN4700-V64 Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com> --------- Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

ayurkiv-nvda added the Request for 202311 Branch label Jul 25, 2024

ayurkiv-nvda changed the title ~~Add SKU v64 o32 public~~ [Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 Jul 25, 2024

ayurkiv-nvda added the Request for 202405 Branch label Jul 25, 2024

ayurkiv-nvda requested review from stephenxs and DavidZagury July 25, 2024 10:44

DavidZagury reviewed Jul 25, 2024

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stephenxs reviewed Jul 26, 2024

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stephenxs approved these changes Jul 27, 2024

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ayurkiv-nvda added 6 commits July 29, 2024 14:28

[Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64

5922026

Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

Update buffers

b871fdb

Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

Use default egress lossless pool size for SN4700 for Mellanox-SN4700-…

af279fe

…O32 and Mellanox-SN4700-V64 Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

[Mellanox] Enable CMIS host mgmt on Mellanox-SN4700-O32 and Mellanox-…

37f1b91

…SN4700-V64 SKUs Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

Update buffers with using 300m cable as a max possible length

d84d2ba

Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

[Mellanox] update title definition, add alias/index/speed keyword, re…

a46bd5e

…-link pg_profile_lookup.ini file Signed-off-by: Andriy Yurkiv <ayurkiv@nvidia.com>

ayurkiv-nvda force-pushed the add_sku_V64_O32_public branch from 1384c0f to a46bd5e Compare July 29, 2024 11:30

DavidZagury approved these changes Jul 29, 2024

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dprital reviewed Aug 1, 2024

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dprital suggested changes Aug 1, 2024

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bingwang-ms approved these changes Aug 5, 2024

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dprital approved these changes Aug 5, 2024

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yxieca added Approved for 202311 Branch Approved for 202405 Branch and removed Approved for 202311 Branch Approved for 202405 Branch labels Aug 5, 2024

yxieca merged commit 978fb9f into sonic-net:master Aug 5, 2024
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yxieca added Approved for 202311 Branch Approved for 202405 Branch labels Aug 5, 2024

mssonicbld mentioned this pull request Aug 5, 2024

[action] [PR:19681] [Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 (#19681) #19822

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[action] [PR:19681] [Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 (#19681) #19823

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[Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 #19681

[Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 #19681

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[Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 #19681

[Mellanox]Adding SKU Mellanox-SN4700-O32 and Mellanox-SN4700-V64 #19681

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ayurkiv-nvda commented Jul 25, 2024 • edited Loading

Why I did it

Work item tracking

How I did it

How to verify it

Which release branch to backport (provide reason below if selected)

Tested branch (Please provide the tested image version)

Description for the changelog

Link to config_db schema for YANG module changes

A picture of a cute animal (not mandatory but encouraged)

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