[chassis-packet/multi-asic] Sort the front panel interface name and u…

…pdate t2 topology (#4623)

Added following changes:-

 1>In case of multi-asic front panel port numbering need not be continuous in
  one ASIC so we need to to sort interface name across ASIC. Added support
  of sort of front panel interface name and corresponding asic name.


  2> Update T2 topology port-connectivity/configuration so to work packet based chassis
  since ports are not continuous in a given ASIC. 
  Old Topology (on each LC) :  { 8 Port Channel  and 8 Router Port Interface }
  New Topology (on each LC) : { 6 Port-Channel, Router Port, Port Channel, Router Port , Port-Channel, 6 Router-Port }

How I Verify:-
Verify minigraph generation for both single/multi-asic

ansible/library/port_alias.py

@@ -99,7 +99,7 @@ def get_portmap(self, asic_id=None, include_internal=False,
         aliasmap = {}
         portspeed = {}
         # Front end interface asic names
-        front_panel_asic_ifnames = []
+        front_panel_asic_ifnames = {}
         # All asic names
         asic_if_names = []
         sysports = []
@@ -118,6 +118,7 @@ def get_portmap(self, asic_id=None, include_internal=False,
         speed_index = -1
         role_index = -1
         asic_name_index = -1
+        port_index = -1
         while len(lines) != 0:
             line = lines.pop(0)
             if re.match('^#', line):
@@ -139,6 +140,8 @@ def get_portmap(self, asic_id=None, include_internal=False,
                             port_core_portid_index = index
                         if 'numvoq' in text:
                             num_voq_index = index
+                        if 'index' in text:
+                            port_index = index
             else:
                 #added support to parse recycle port
                 if re.match('^Ethernet', line) or re.match('^Recirc', line):
@@ -160,12 +163,12 @@ def get_portmap(self, asic_id=None, include_internal=False,
                     add_port = False
                     if role == 'Ext' or (role == "Int" and include_internal):
                         add_port = True
-                        aliases.append(alias)
+                        aliases.append((alias, -1 if port_index == -1 or len(mapping) <= port_index else mapping[port_index]))
                         portmap[name] = alias
                         aliasmap[alias] = name
                         if role == "Ext" and (asic_name_index != -1) and (len(mapping) > asic_name_index):
                             asicifname = mapping[asic_name_index]
-                            front_panel_asic_ifnames.append(asicifname)
+                            front_panel_asic_ifnames[alias] = asicifname
                     if (asic_name_index != -1) and (len(mapping) > asic_name_index):
                         asicifname = mapping[asic_name_index]
                         asic_if_names.append(asicifname)
@@ -223,8 +226,8 @@ def main():
         aliasmap = {}
         portspeed = {}
         sysports = []
-        # ASIC interface names of front panel interfaces
-        front_panel_asic_ifnames = []
+        # Map of ASIC interface names to front panel interfaces
+        front_panel_asic_ifnames = {}
         # { asic_name: [ asic interfaces] }
         asic_if_names = {}
 
@@ -233,7 +236,7 @@ def main():
                                            'port_name_map': portmap,
                                            'port_alias_map': aliasmap,
                                            'port_speed': portspeed,
-                                           'front_panel_asic_ifnames': front_panel_asic_ifnames,
+                                           'front_panel_asic_ifnames': [],
                                            'asic_if_names': asic_if_names,
                                            'sysports': sysports})
            return
@@ -286,17 +289,20 @@ def main():
             if portspeed_asic is not None:
                 portspeed.update(portspeed_asic)
             if front_panel_asic is not None:
-                front_panel_asic_ifnames.extend(front_panel_asic)
+                front_panel_asic_ifnames.update(front_panel_asic)
             if asicifnames_asic is not None:
                 asic = 'ASIC' + str(asic_id)
                 asic_if_names[asic] = asicifnames_asic
             if sysport_asic is not None:
                 sysports.extend(sysport_asic)
-        module.exit_json(ansible_facts={'port_alias': aliases,
+
+        # Sort the Interface Name needed in multi-asic
+        aliases.sort(key=lambda x: int(x[1]))
+        module.exit_json(ansible_facts={'port_alias': [k[0] for k in aliases],
                                         'port_name_map': portmap,
                                         'port_alias_map': aliasmap,
                                         'port_speed': portspeed,
-                                        'front_panel_asic_ifnames': front_panel_asic_ifnames,
+                                        'front_panel_asic_ifnames': [front_panel_asic_ifnames[k[0]] for k in aliases] if front_panel_asic_ifnames else [],
                                         'asic_if_names': asic_if_names,
                                         'sysports': sysports})
     except (IOError, OSError) as e: