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1. minimig-de0_cv minimig-de0_cv Public

   Verilog

2. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   Assembly

3. scr1 scr1 Public

   Forked from syntacore/scr1

   SCR1 is a high-quality open-source RISC-V MCU core in Verilog

   SystemVerilog

4. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

   SystemVerilog

5. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog

6. cv32e40x cv32e40x Public

   Forked from openhwgroup/cv32e40x

   4 stage, in-order, compute RISC-V core based on the CV32E40P

   SystemVerilog