i2c: properly handle bus errors

In send_byte() wait for TX fifo empty before returning Ok. It would be
better to wait for end of transmission, but there is no such field in
I2C status register.

In recv_byte() return Err if error condition detected while waiting for
byte.

Before starting new transaction ensure that both TX and RX buffers are
empty. There are some corner cases where something may be there.

src/i2c.rs

@@ -183,6 +183,12 @@ where
     }
 
     fn start_transfer(&mut self, addr: u8, len: usize, direction: RD_WRN_A) {
+        // Ensure that TX/RX buffers are empty
+        self.i2c.isr.write(|w| w.txe().set_bit());
+        while self.i2c.isr.read().rxne().bit_is_set() {
+            self.i2c.rxdr.read();
+        };
+
         self.i2c.cr2.write(|w|
             w
                 // Start transfer
@@ -217,13 +223,26 @@ where
             } else if isr.nackf().bit_is_set() {
                 self.i2c.icr.write(|w| w.nackcf().set_bit());
                 return Err(Error::Nack);
+            } else if isr.txe().bit_is_set() {
+                return Ok(());
             }
-            return Ok(());
         }
     }
 
     fn recv_byte(&self) -> Result<u8, Error> {
-        while self.i2c.isr.read().rxne().bit_is_clear() {}
+        while self.i2c.isr.read().rxne().bit_is_clear() {
+            let isr = self.i2c.isr.read();
+            if isr.berr().bit_is_set() {
+                self.i2c.icr.write(|w| w.berrcf().set_bit());
+                return Err(Error::BusError);
+            } else if isr.arlo().bit_is_set() {
+                self.i2c.icr.write(|w| w.arlocf().set_bit());
+                return Err(Error::ArbitrationLost);
+            } else if isr.nackf().bit_is_set() {
+                self.i2c.icr.write(|w| w.nackcf().set_bit());
+                return Err(Error::Nack);
+            }
+        }
 
         let value = self.i2c.rxdr.read().rxdata().bits();
         Ok(value)