LinkedTimer: Implement initial version

[dbrgn]

Implementation of #114.

A LinkedTimer impl is initialized with two hardware timers (either TIM2/TIM3 or TIM21/TIM22). The two timers are configured in master/slave mode so that an overflow of the master timer triggers an update on the slave timer. This way, two 16 bit timers can be combined to a single 32 bit timer. (The STM32L0 does not have 32 bit timers.)

Such a linked timer allows implementing the Monotonic trait for the RTIC scheduler with high timer precision.

Right now the implementation does not add logic for detecting an overflow, that is left to the user. Furthermore, no prescaler is configured. And not all possible timer combinations have been implemented.

An example is provided (tested on the STM32L071KBTx). Here's the serial output:

Starting example
Init TIM2/TIM3...
Init TIM21/TIM22...
TIM2/TIM3    count   26790878 (msb=408 lsb=52211 Δ26790878 53581 kHz)
TIM21/TIM22  count   11182841 (msb=170 lsb=41743 Δ11182841 22365 kHz)
TIM2/TIM3    count   34790917 (msb=530 lsb=56858 Δ8000039 16000 kHz)
TIM21/TIM22  count   19166170 (msb=292 lsb=29680 Δ7983329 15966 kHz)
TIM2/TIM3    count   42790960 (msb=652 lsb=61509 Δ8000043 16000 kHz)
TIM21/TIM22  count   27166218 (msb=414 lsb=34336 Δ8000048 16000 kHz)
TIM2/TIM3    count   50791003 (msb=775 lsb=624 Δ8000043 16000 kHz)
TIM21/TIM22  count   35132916 (msb=536 lsb=5642 Δ7966698 15933 kHz)
TIM2/TIM3    count   58791046 (msb=897 lsb=5275 Δ8000043 16000 kHz)
...

Let me know whether this is useful, and whether the implementation looks correct. This was my first STM32 timer deep-dive, I spent quite a few hours looking through the reference manual to figure out how to link timers 🙂

The relevant information in the reference manual (RM0377) is in section 16.3.15 "Timer synchronization". Here's the section that describes timer linking:

[hannobraun]

Thanks you, @dbrgn! I don't have the time for a full review, but I took a quick look and it looks good. Since it looks like you've done your homework here, I'd be happy to approve and merge, unless anyone else objects.

CI is failing though, due to the RTFM -> RTIC rename. It probably makes sense to fix this in a separate PR, then rebase this one.

[dbrgn]

CI is failing though, due to the RTFM -> RTIC rename. It probably makes sense to fix this in a separate PR, then rebase this one.

Yep, I meant to do that (but it was already late yesterday). I'll provide a PR tonight, afterwards we can rebase.

[dbrgn]

Updated, now with reset 🙂

I discovered that this cannot be used for RTIC (since the RTIC monotonic timer must be initialized statically), but it may be useful nevertheless.

[hannobraun]

Looks like this was left un-merged for no good reason. Merging.