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Release 2.3.0 (#21)
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* Release 2.3.0

* Update doc/CHANGELOG.md

Co-authored-by: Teque5 <teque5@gmail.com>

* Update doc/ARTY_A7.md

Co-authored-by: Teque5 <teque5@gmail.com>

* Update doc/CHANGELOG.md

Co-authored-by: Teque5 <teque5@gmail.com>

* Update examples/README.md

Co-authored-by: Teque5 <teque5@gmail.com>

---------

Co-authored-by: Teque5 <teque5@gmail.com>
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@ooterness @Teque5
ooterness and Teque5 authored Feb 15, 2023
1 parent a83d764 commit bbba3e4
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174 changes: 100 additions & 74 deletions Jenkinsfile
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// Copyright 2020, 2021, 2022 The Aerospace Corporation
// Copyright 2020, 2021, 2022, 2023 The Aerospace Corporation
//
// This file is part of SatCat5.
//
Expand Down Expand Up @@ -99,6 +99,7 @@ pipeline {
}

environment {
BUILD_AGENT = 'docker && !gpuboss2'
BUILD_TYPE = build_type()
DOCKER_REG = 'e3-devops.aero.org'
}
Expand All @@ -107,7 +108,7 @@ pipeline {
stage('SW-Test') {
parallel {
stage('Linter') {
agent { label 'docker' }
agent { label env.BUILD_AGENT }
steps {
sh_node 'echo $BRANCH_NAME : $BUILD_TYPE'
sh_node 'echo $DOCKER_REG'
Expand All @@ -119,13 +120,13 @@ pipeline {
}
}
stage('Tools') {
agent { label 'docker' }
agent { label env.BUILD_AGENT }
steps {
docker_devtool 'make sw_tools'
}
}
stage('Unit tests') {
agent { label 'docker' }
agent { label env.BUILD_AGENT }
steps {
docker_devtool 'make sw_python'
docker_devtool 'make sw_coverage'
Expand All @@ -151,37 +152,45 @@ pipeline {
}
}
}
// Limit to three simultaneous Vivado builds.
// TODO: Generate simulation stages automatically?
// Note: Auto-generated stages cannot use a declarative pipeline.
// https://devops.stackexchange.com/questions/9887/how-to-define-dynamic-parallel-stages-in-a-jenkinsfile
// https://www.incredibuild.com/blog/jenkins-parallel-builds-jenkins-distributed-builds
stage('Sims 0') {
when { expression { env.BUILD_TYPE == 'hdl' } }
agent { label 'docker' }
steps { run_sim(0, 4) }
agent { label env.BUILD_AGENT }
steps { run_sim(0, 3) }
}
stage('Sims 1') {
when { expression { env.BUILD_TYPE == 'hdl' } }
agent { label 'docker' }
steps { run_sim(1, 4) }
agent { label env.BUILD_AGENT }
steps { run_sim(1, 3) }
}
stage('Sims 2') {
when { expression { env.BUILD_TYPE == 'hdl' } }
agent { label 'docker' }
steps { run_sim(2, 4) }
}
stage('Sims 3') {
when { expression { env.BUILD_TYPE == 'hdl' } }
agent { label 'docker' }
steps { run_sim(3, 4) }
agent { label env.BUILD_AGENT }
steps { run_sim(2, 3) }
}
}
}
stage('HW-Build') {
stage('HW-Build1') {
when { expression { env.BUILD_TYPE == 'hdl' } }
parallel {
// Limit to three simultaneous Vivado builds.
stage('AC701-SGMII') {
agent { label env.BUILD_AGENT }
steps {
docker_vivado_2016_3 'make proto_v1_sgmii'
check_vivado_build 'examples/ac701_proto_v1/ac701_proto_v1/ac701_proto_v1.runs'
dir('examples/ac701_proto_v1/switch_proto_v1_sgmii/switch_proto_v1_sgmii.runs/impl_1') {
archive_zip('switch_top_ac701_sgmii.zip', './*.rpt')
archiveArtifacts artifacts: 'switch_top_ac701_sgmii.bit'
}
}
}
stage('Arty-35T') {
agent { label 'docker' }
agent { label env.BUILD_AGENT }
steps {
docker_vivado_2016_3 'make arty_35t'
check_vivado_build 'examples/arty_a7/switch_arty_a7_35t/switch_arty_a7_35t.runs'
Expand All @@ -192,7 +201,7 @@ pipeline {
}
}
stage('Arty-Managed') {
agent { label 'docker' }
agent { label env.BUILD_AGENT }
steps {
docker_vivado_2019_1 'make arty_managed_35t'
check_vivado_build 'examples/arty_managed/arty_managed_35t/arty_managed_35t.runs'
Expand All @@ -207,8 +216,56 @@ pipeline {
}
}
}
// Other FPGA platforms:
stage('MPF-Splash') {
agent { label env.BUILD_AGENT }
when { expression { false } } // Disabled due to licensing issues.
steps {
catchError(buildResult: 'SUCCESS', stageResult: 'UNSTABLE') { retry(2) {
docker_libero './examples/mpf_splash/make_project.sh'
} }
dir('examples/mpf_splash/switch_mpf_splash_rgmii_100T/designer/switch_top_mpf_splash_rgmii') {
archiveArtifacts artifacts: '*has_violations,*violations*.xml,*timing_constraints_coverage.xml'
}
dir('examples/mpf_splash/switch_mpf_splash_rgmii_100T') {
archiveArtifacts artifacts: 'switch_mpf_splash_rgmii_100T.job'
archiveArtifacts artifacts: 'switch_mpf_splash_rgmii_100T_job.digest'
}
}
}
stage('iCE40-rmii-serial') {
agent { label env.BUILD_AGENT }
steps {
docker_yosys 'make ice40_rmii_serial'
dir('examples/ice40_hx8k/switch_top_rmii_serial_adapter') {
archiveArtifacts artifacts: 'switch_top_rmii_serial_adapter.bin'
}
}
}
}
}
stage('HW-Build2') {
when { expression { env.BUILD_TYPE == 'hdl' } }
parallel {
// Limit to three simultaneous Vivado builds.
stage('AC701-Router') {
agent { label env.BUILD_AGENT }
steps {
docker_vivado_2019_1 'make ac701_router'
check_vivado_build 'examples/ac701_router/router_ac701/router_ac701.runs'
dir('examples/ac701_router') {
archiveArtifacts artifacts: 'router_ac701/*.svg'
}
dir('examples/ac701_router/router_ac701/router_ac701.runs') {
archive_zip('router_ac701_wrapper.zip', '*/*.rpt')
}
dir('examples/ac701_router/router_ac701/router_ac701.runs/impl_1') {
archiveArtifacts artifacts: 'router_ac701_wrapper.bit'
}
}
}
stage('NetFPGA') {
agent { label 'docker' }
agent { label env.BUILD_AGENT }
steps {
docker_vivado_2019_1 'make netfpga'
check_vivado_build 'examples/netfpga/netfpga/netfpga.runs'
Expand All @@ -223,21 +280,9 @@ pipeline {
}
}
}
stage('VC707-ClkSynth') {
agent { label 'docker' }
steps {
docker_vivado_2019_1 'make vc707_clksynth'
check_vivado_build 'examples/vc707_clksynth/clock_synth/clock_synth.runs'
dir('examples/vc707_clksynth/clock_synth') {
archiveArtifacts artifacts: 'clock_synth.runs/impl_1/runme.log'
}
dir('examples/vc707_clksynth/clock_synth/clock_synth.runs/impl_1') {
archiveArtifacts artifacts: 'clock_synth.bit'
}
}
}
stage('VC707-Managed') {
agent { label 'docker' }
agent { label env.BUILD_AGENT }
when { expression { false } } // Disabled due to licensing issues.
steps {
docker_vivado_2019_1 'make vc707_managed'
check_vivado_build 'examples/vc707_managed/vc707_managed/vc707_managed.runs'
Expand All @@ -252,55 +297,36 @@ pipeline {
}
}
}
stage('AC701-SGMII') {
agent { label 'docker' }
steps {
docker_vivado_2016_3 'make proto_v1_sgmii'
check_vivado_build 'examples/ac701_proto_v1/ac701_proto_v1/ac701_proto_v1.runs'
dir('examples/ac701_proto_v1/switch_proto_v1_sgmii/switch_proto_v1_sgmii.runs/impl_1') {
archive_zip('switch_top_ac701_sgmii.zip', './*.rpt')
archiveArtifacts artifacts: 'switch_top_ac701_sgmii.bit'
}
}
}
stage('AC701-Router') {
agent { label 'docker' }
}
}
stage('HW-Build3') {
when { expression { env.BUILD_TYPE == 'hdl' } }
parallel {
// Limit to three simultaneous Vivado builds.
stage('VC707-ClkSynth') {
agent { label env.BUILD_AGENT }
steps {
docker_vivado_2019_1 'make ac701_router'
check_vivado_build 'examples/ac701_router/router_ac701/router_ac701.runs'
dir('examples/ac701_router') {
archiveArtifacts artifacts: 'router_ac701/*.svg'
docker_vivado_2019_1 'make vc707_clksynth'
check_vivado_build 'examples/vc707_clksynth/vc707_clksynth/vc707_clksynth.runs'
dir('examples/vc707_clksynth/vc707_clksynth') {
archiveArtifacts artifacts: 'vc707_clksynth.runs/impl_1/runme.log'
}
dir('examples/ac701_router/router_ac701/router_ac701.runs') {
archive_zip('router_ac701_wrapper.zip', '*/*.rpt')
}
dir('examples/ac701_router/router_ac701/router_ac701.runs/impl_1') {
archiveArtifacts artifacts: 'router_ac701_wrapper.bit'
dir('examples/vc707_clksynth/vc707_clksynth/vc707_clksynth.runs/impl_1') {
archiveArtifacts artifacts: 'vc707_clksynth.bit'
}
}
}
stage('MPF-Splash') {
agent { label 'docker' }
stage('ZCU208-ClkSynth') {
agent { label env.BUILD_AGENT }
when { expression { false } } // Disabled due to licensing issues.
steps {
catchError(buildResult: 'SUCCESS', stageResult: 'UNSTABLE') { retry(2) {
docker_libero './examples/mpf_splash/make_project.sh'
} }
dir('examples/mpf_splash/switch_mpf_splash_rgmii_100T/designer/switch_top_mpf_splash_rgmii') {
archiveArtifacts artifacts: '*has_violations,*violations*.xml,*timing_constraints_coverage.xml'
docker_vivado_2020_2 'make zcu208_clksynth'
check_vivado_build 'examples/zcu208_clksynth/zcu208_clksynth/zcu208_clksynth.runs'
dir('examples/zcu208_clksynth/zcu208_clksynth') {
archiveArtifacts artifacts: 'zcu208_clksynth.runs/impl_1/runme.log'
}
dir('examples/mpf_splash/switch_mpf_splash_rgmii_100T') {
archiveArtifacts artifacts: 'switch_mpf_splash_rgmii_100T.job'
archiveArtifacts artifacts: 'switch_mpf_splash_rgmii_100T_job.digest'
}
}
}
stage('iCE40-rmii-serial') {
agent { label 'docker' }
steps {
docker_yosys 'make ice40_rmii_serial'
dir('examples/ice40_hx8k/switch_top_rmii_serial_adapter') {
archiveArtifacts artifacts: 'switch_top_rmii_serial_adapter.bin'
dir('examples/zcu208_clksynth/zcu208_clksynth/zcu208_clksynth.runs/impl_1') {
archiveArtifacts artifacts: 'zcu208_clksynth.bit'
}
}
}
Expand Down
6 changes: 6 additions & 0 deletions Makefile
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Expand Up @@ -106,6 +106,11 @@ vc707_clksynth:
vc707_managed:
@cd examples/vc707_managed && ${VIVADO_RUN} create_all.tcl

# ZCU208 example design
.PHONY: zcu208_clksynth
zcu208_clksynth:
@cd examples/zcu208_clksynth && ${VIVADO_RUN} create_vivado.tcl

# Example design for ZedBoard.
.PHONY: zed_converter
zed_converter:
Expand All @@ -129,6 +134,7 @@ log_viewer:
# Build each of the C++ example tools.
.PHONY: sw_tools
sw_tools:
@cd examples/zcu208_clksynth/config_tool && make all
@cd test/log_viewer && make all

# Build and run software tests
Expand Down
2 changes: 1 addition & 1 deletion doc/ARTY_A7.md
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Expand Up @@ -24,7 +24,7 @@ Follow these steps to build the design and deploy to your Arty A7 board.
* Navigate to the SatCat5 folder. e.g., `cd path/to/satcat5`
* Run either `set argv 35t` or `set argv 100t` to select the appropriate hardware variant.
* Then run the following commands:
```
```bash
cd examples/arty_a7
source create_project_arty_a7.tcl
```
Expand Down
12 changes: 11 additions & 1 deletion doc/CHANGELOG.md
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Expand Up @@ -78,9 +78,19 @@ This log will be updated for each new release, but may not reflect the latest de
* Tooltips for all IP-core configuration parameters.
* Bug-fixes for router_inline and MDIO device-driver.

## v2.3.0

* New `zcu208_clksynth` example design and associated device drivers.
* New `sgmii_lvds` IP-core.
* Port mode (port_serial_auto) is now CPU-configurable.
* Refactor C++ test utilities for better code-reuse.
* Update cfg::NetworkStats driver to allow remote access.
* Update poll::OnDemand main loop to prevent orphaned tasks.
* Update documenation and TCL scripts.

# Copyright Notice

Copyright 2019, 2020, 2021, 2022 The Aerospace Corporation
Copyright 2019, 2020, 2021, 2022, 2023 The Aerospace Corporation

This file is part of SatCat5.

Expand Down
11 changes: 10 additions & 1 deletion examples/README.md
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Expand Up @@ -91,6 +91,15 @@ It also contains a Microblaze processor and several ConfigBus peripherals.

Note that this design requires the "AVB" license for the Xilinx TEMAC IP-core, due to the use of PTP features.

# zcu208_clksynth

Target: [Xilinx ZCU208 development board](https://www.xilinx.com/products/boards-and-kits/zcu208.html)

Like the `vc707_clksynth` demo, this example design is used to verify performance of the Vernier-PLL system.
In this demo, a Vernier-PLL is used to synthesize a 125 MHz sine wave.
Use of sine waves instead of discrete-sampled square waves avoids discrete-time quantization error.
In theory, this allows accuracy and jitter measurements on picosecond time-scales.

# zed_converter

Target: [ZedBoard Zynq-7000 Development Board](https://digilent.com/reference/programmable-logic/zedboard/start)
Expand All @@ -99,7 +108,7 @@ This design connects the Zynq PS Ethernet port to a PMOD Ethernet-over-SPI/UART

# Copyright Notice

Copyright 2021, 2022 The Aerospace Corporation
Copyright 2021, 2022, 2023 The Aerospace Corporation

This file is part of SatCat5.

Expand Down
4 changes: 2 additions & 2 deletions examples/arty_managed/sdk_src/main.cc
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@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////////
// Copyright 2021, 2022 The Aerospace Corporation
// Copyright 2021, 2022, 2023 The Aerospace Corporation
//
// This file is part of SatCat5.
//
Expand Down Expand Up @@ -164,7 +164,7 @@ class HousekeepingTimer : satcat5::poll::Timer
// Optionally log the SatCat5 port status register.
// (Refer to port_rmii and port_statistics for more info.)
if (DEBUG_PORT_STATUS) {
u32 status = traffic_stats.get_port(PORT_IDX_RMII)->status;
u32 status = traffic_stats.get_port(PORT_IDX_RMII).status;
Log(satcat5::log::DEBUG, "RMII status").write(status);
}
}
Expand Down
4 changes: 2 additions & 2 deletions examples/netfpga/sdk_src/main.cc
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@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////////
// Copyright 2022 The Aerospace Corporation
// Copyright 2022, 2023 The Aerospace Corporation
//
// This file is part of SatCat5.
//
Expand Down Expand Up @@ -123,7 +123,7 @@ class HousekeepingTimer : satcat5::poll::Timer
if (DEBUG_PORT_STATUS) {
Log log(LOG_DEBUG, "Port status");
for (unsigned a = 0 ; a < eth_switch.port_count() ; ++a) {
log.write(traffic_stats.get_port(a)->status);
log.write(traffic_stats.get_port(a).status);
}
}
}
Expand Down
4 changes: 2 additions & 2 deletions examples/vc707_clksynth/create_vivado.tcl
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Expand Up @@ -25,8 +25,8 @@ cd [file normalize [file dirname [info script]]]

# Set project-level properties depending on the selected board.
set target_part "XC7VX485TFFG1761-2"
set target_proj "clock_synth"
set target_top "clock_synth"
set target_proj "vc707_clksynth"
set target_top "vc707_clksynth"
set constr_synth "vc707_synth.xdc"
set constr_impl "vc707_impl.xdc"
set override_postbit ""
Expand Down
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