Ampere Altra Mt. Jade: Upstream bugfixes, improvements, and features #193

This updates the platform info HOB structure to align with the latest Ampere Altra Software Release Package (SRP) revision 2.10. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This updates the NVPARAM definitions to align with the latest Ampere Altra Software Release Package (SRP) revision 2.10. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The current default setting of the hardware EINJ in the VFR is not consistent with the NVPARAM. And, the setting should be disabled by default. This is to correct the DEFAULT flag for the HW EINJ option in the VFR. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The existing DDR CE threshold feature is designed for both BMC and OS reporting. However, some customers wish to report exclusively to BMC while continuing to report all errors to the OS. The new NVPARAM "CE threshold control (THC)" has been introduced to address this scenario. THC = 0: Report to both BMC and OS. THC = 1: Report to both BMC. Default value is 0. If CE window is enabled and THC is set to 0, the DDR CE threshold option will be shown in the UEFI Setup Menu. Otherwise, the configuration option is hidden. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

It is recommended that Symbol be used exclusively for x4 DIMMs. For non x4 DIMMs, it is advisable to select SECDED. This introduces an Auto mode in the ECC mode option, enabling automatic detection of the device width and selection of the recommended mode. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

To get rid of hardware dependency on a chosen RTC chip in the common SMpro/PMpro firmware, the SMpro will get the RTC datetime from UEFI through a mailbox interface instead of accessing directly to the platform RTC chip. This patch is to hook this date configuration to the runtime RTC library so the SMpro datetime is always updated once having changes from users both at boot time and runtime. Note that the CPU performance might be impacted with lack of this support. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

EDK2 firmware currently reports only the UEFI firmware booting stage and excludes the OS booting stage. The OS booting stage starts with the Boot Device Selection (BDS) phase and concludes with the Exit Boot Services event, as per the Ampere Altra SoC BMC Interface specification. Consequently, the endpoint for the UEFI firmware booting stage is designated as EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEXT, and for the OS booting stage, it is EFI_SW_BS_PC_EXIT_BOOT_SERVICES. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This adds the LED device to the ACPI DSDT table to support the hotplug attention indicator control requested from Linux through ACPI. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This patch is to initialize the UART2 designed for WinDbg. Also, drops the initialization of UART0 as it's been done in the Trusted Firmware-A (aka TF-A) for printing the early boot information. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The Ampere Altra processor has a unique MPIDR structure that accommodates the socket ID within the CPU core information. However, the existing GET_MPID() is incompatible, thus this patch introduces Ampere-specific MPIDR definitions. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This patch updates the ARM_CORE_INFO.Mpidr to align with the new definition specific to Ampere. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This patch updates the MPIDR entries in the MADT and SRAT ACPI tables to align with the MPIDR values produced in ARM_CORE_INFO. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This patch is to advertise the ATS support in the Root Complex entries of the IORT table as Altra supports it. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The commit 32ac6cc ("JadePkg/AcpiTables: Update ACPI table of Altra for the new DSU PMU spec" has changed the DSU node path. This patch aims to rectify its path for _STAT patching. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The system is consistently configured to build 2-sockets memory map, irrespective of the slave's status, whether disabled or enabled. This configuration leads to a kernel crash when the slave is inactive. This patch aims to resolve this problem by properly patching the MMIO resource for 1P system. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

By default, ACPI DSDT defines the MMIO32 resource of RCs for 2P platform excluding RCA0/1 used for CCIX. For 1P platform, MMIO32 resource of other RCs should be modified but MMIO32 resource of RCA0/1 should be 256MB by default. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The size of the allocated memory for the BERT Crash Dump is sizeof (APEI_CRASH_DUMP_BERT_ERROR), 0x27F8D. But, currently, the amount of memory copied to a specified location as defined ACPI BERT table is BERT_DDR_LENGTH (0x50000). This is more than the memory allocated. To fix this security hole, the memory copied should be the same as the memory allocated. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

BERT error record must be persistent across boots on catastrophic errors until the BMC and UEFI have had a chance to retrieve the information. To support this, the BERT is sectioned off into two different sections. * BERT Error Record (sectors 0-61 => 4KB * 62 = 248KB) * BERT Error Record Status (sectors 79 => 4KB * 1 = 4KB) The BERT Error Record Status section will be updated, by UEFI, SCP and BMC on the current state of the BERT Error Record. The following parameters will keep the state of the BERT Error Record * DefaultBert Indicate Default Bert Error Record Present. Set by UEFI on boot and cleared by SCP on shutdown, reboot, or crash. If UEFI sees this parameter set it will populate a default BERT to be reported to the OS. * Overflow The original BERT Error Record was over written by a subsequent BERT Error Record. Set by SCP if PendingUefi or PendingBMC was set and to be cleared by UEFI if PendingUefi and PendingBMC are cleared. * PendingUefi Indicate Pending UEFI detection of BERT Error Record. Set by SCP and to be cleared by UEFI. If parameter set UEFI will populate the full BERT error record to be reported to the OS. * PendingBmc Indicate Pending BMC detection of BERT Error Record. Set by SCP and to be cleared by BMC. The BERT Error Record can be read from the BMC via the following NVPARAM addresses: * 0x130000 - Read the beginning of BERT header * 0x130030 - Read BERT Error Record revision The BERT Error Record Status can be read from the BMC via the following NVPARAM addresses: * 0x17F000 - Read the beginning of AMPERE GUID * 0x17F010 - Read BERT Error Record Status revision * 0x17F018 - Read BERT Error Record Parameters NVPARAM at 0x17f018: Param: 0x01010101 | | | `--DefaultBert | | `----Overflow | `------PendingUefi `--------PendingBmc To clear PendingBmc, set 0x00010101 to the Error Record Parameter (0x17F018). Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This implements ACPI BDAT table with UEFI DIMM SPD RAW Data Schema 7. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This introduces an option to enable System Level Cache (SLC) as L3 cache, which can enhance performance for certain applications. This feature is active and enabled by default in 1P monolithic mode. Additionally, the SubNUMA mode cannot be altered when the SLC as L3 cache option is enabled. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This adds the size of the SLC/L3 cache in the Platform Information screen when the SLC as L3 cache is enabled. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This update enhances the ACPI PPTT table by reducing the table size, allowing each processor node to reference the same L1 and L2 cache nodes. It also enables the generation of the PPTT table based on the number of active cores. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This adds the SLC node to the ACPI PPTT table when the SLC as L3 cache configuration is enabled. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This add the System Level Cache (SLC) information to the SMBIOS Type 7 when the SLC as L3 cache configuration is enabled in the CPU Configuration screen. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This supports retrieving FRU information from BMC via IPMI SSIF interface for the SMBIOS Type 1,2,3. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This adds functions for getting the information of CPU SKU and ECID (serial number) from platform HOB. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This implements OemUpdateSmbiosInfo() for processor information such as version, serial number, and part number. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The CPU frequency in the platform is populated in MHz. The scale factor is unncessary. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

In the FailSafe context, there is a field that indicates which setting is being used to boot (BOOT_LAST_KNOWN_SETTINGS, BOOT_DEFAULT_SETTINGS, BOOT_NORMAL). On the SCP and TF-A side, they will check their NVPARAM for FailSafe (NV_SI_PMPRO_FAILURE_FAILSAFE - NV_SI_ATF_FAILURE_FAILSAFE) to determine which setting to use. If a FailSafe event occurs at SCP or TF-A, it is the responsibility of UEFI during the DXE phase to clear the FailSafe context to ensure normal behavior. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The SMBIOS memory table (type 16, 17, and 19) has been integrated into the SmbiosPlatformDxe for the refactor of the platform SMBIOS implementation. So, this patch is to remove the old implementation. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The I2C controller in the slave socket is connected to the IO expander for determining the usage of the system slot. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

The IOExpanderLib supports reading the IO expander via I2C on Mt. Jade. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

This patch aims to update the SMBIOS type 9 during UEFI booting such as PCI segment of the slot, slot usage, based on the data retrieved from IO expander. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

According to the SMBIOS specification, for multi-core processors, the cache size for the different levels of the cache (L1, L2, L3) is the total amount of cache per level per processor socket. The current ArmPkg/SMBIOS framework only constructs the cache size for a core. This patch aims to correct it. Additionally, this corrects the cache error correction type and cache configuration. Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Ampere Altra Mt. Jade: Upstream bugfixes, improvements, and features #193

Ampere Altra Mt. Jade: Upstream bugfixes, improvements, and features #193

Commits on Sep 17, 2024