Pass ILM SDCs upwards through hierarchical flow

[harrisonliew]

ILM SDCs were not getting read during parent synthesis. These SDCs predominantly have set_case_analysis and set_annotated_transition commands, which are required in some cases to properly choose the proper timing mode in lib files.

Related PRs / Issues

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• Change to core Hammer
• Change to a Hammer plugin
• Other

Contributor Checklist:

• Did you set master as the base branch?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you update the poetry.lock file if you updated the requirements in pyproject.toml?
• (If applicable) Did you add a unit test demonstrating the PR?
• (If applicable) Did you run this through the e2e integration tests?
• (If applicable) Did you update the submodules in e2e/ if this feature depends on updated plugins?

[SeahK]

syn-ChipTop timing looks alright with this fix! Thanks :)