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vlsi.inputs.supplies.power/ground.pin
to.pins
. This generates CPFs with acreate_global_connection
from single net to multiple pinspower_straps_options.by_tracks.power_nets
setting. This controls which supply nets power straps are generated for. The default uses all supplies, but this is not always desiredvlsi.input.supplies.power.voltage
field. The existing system would always create the power_nets with the samevlsi.inputs.supplies.VDD
voltage. This enables per-supply voltage setting.Related PRs / Issues
Type of change:
Impact:
Contributor Checklist:
master
as the base branch?poetry.lock
file if you updated the requirements inpyproject.toml
?e2e/
if this feature depends on updated plugins?