Merge pull request #137 from vhda/verilog/define-with-equal

verilog: Include define argument with equal sign in tests
universal-ctags · Nov 23, 2014 · 35ccf0d · 35ccf0d
2 parents 2cdd4c9 + b0434da
commit 35ccf0d
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diff --git a/Units/verilog-2001.d/expected.tags b/Units/verilog-2001.d/expected.tags
@@ -1,5 +1,6 @@
 DEFINE	input.v	/^`define DEFINE$/;"	c
 DEF_VALUE	input.v	/^`define DEF_VALUE   1'd100$/;"	c
+DEF_WITH_EQ	input.v	/^`define DEF_WITH_EQ = 1'd100$/;"	c
 LOCALPARAM	input.v	/^localparam LOCALPARAM = 2**2;$/;"	c	module:mod
 PARAM1	input.v	/^    parameter PARAM1 = 10,$/;"	c	module:mod
 PARAM2	input.v	/^    parameter PARAM2 = 2.0$/;"	c	module:mod

diff --git a/Units/verilog-2001.d/input.v b/Units/verilog-2001.d/input.v
@@ -2,6 +2,7 @@
 // module wrong;
 // endmodule
 `define DEFINE
+`define DEF_WITH_EQ = 1'd100
 `define DEF_VALUE   1'd100
 
 module mod#(

diff --git a/Units/verilog-basic.d/expected.tags b/Units/verilog-basic.d/expected.tags
@@ -1,5 +1,6 @@
 DEFINE	input.v	/^`define DEFINE$/;"	c
 DEF_VALUE	input.v	/^`define DEF_VALUE   1'd100$/;"	c
+DEF_WITH_EQ	input.v	/^`define DEF_WITH_EQ = 1'd100$/;"	c
 PARAM	input.v	/^parameter PARAM = 1;$/;"	c	module:mod
 STATE1	input.v	/^parameter STATE1 = 4'h0,$/;"	c	module:mod
 STATE2	input.v	/^          STATE2 = 4'h1,$/;"	c	module:mod

diff --git a/Units/verilog-basic.d/input.v b/Units/verilog-basic.d/input.v
@@ -2,6 +2,7 @@
 // module wrong;
 // endmodule
 `define DEFINE
+`define DEF_WITH_EQ = 1'd100
 `define DEF_VALUE   1'd100
 
 module mod (