Fix error by repeated generics usage

crates/analyzer/src/handlers/check_expression.rs

@@ -110,7 +110,6 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> {
                         | SymbolKind::TypeDef(_)
                         | SymbolKind::Modport(_)
                         | SymbolKind::Namespace
-                        | SymbolKind::GenericInstance(_)
                         | SymbolKind::ClockDomain
                         | SymbolKind::Test(_) => {
                             self.errors.push(error);
@@ -135,6 +134,7 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> {
                         | SymbolKind::GenericParameter(_)
                         | SymbolKind::StructMember(_)
                         | SymbolKind::UnionMember(_)
+                        | SymbolKind::GenericInstance(_)
                         | SymbolKind::Variable(_) => {}
 
                         SymbolKind::Enum(_) | SymbolKind::Union(_) | SymbolKind::Struct(_) => {
@@ -150,21 +150,33 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> {
                     // Must be a function call
                     let expid = x.expression_identifier.as_ref();
                     if let Ok(rr) = symbol_table::resolve(expid) {
-                        match rr.found.kind {
+                        let is_function = match &rr.found.kind {
                             SymbolKind::Function(_)
                             | SymbolKind::SystemVerilog
                             | SymbolKind::ModportFunctionMember(..)
-                            | SymbolKind::SystemFunction => {}
-                            _ => {
-                                let identifier = rr.found.token.to_string();
-                                let token: TokenRange = x.expression_identifier.as_ref().into();
-                                self.errors.push(AnalyzerError::call_non_function(
-                                    &identifier,
-                                    &rr.found.kind.to_kind_name(),
-                                    self.text,
-                                    &token,
-                                ));
+                            | SymbolKind::SystemFunction => true,
+                            SymbolKind::GenericInstance(x) => {
+                                let base = symbol_table::get(x.base).unwrap();
+                                match base.kind {
+                                    SymbolKind::Function(_)
+                                    | SymbolKind::SystemVerilog
+                                    | SymbolKind::ModportFunctionMember(..)
+                                    | SymbolKind::SystemFunction => true,
+                                    _ => false,
+                                }
                             }
+                            _ => false,
+                        };
+
+                        if !is_function {
+                            let identifier = rr.found.token.to_string();
+                            let token: TokenRange = x.expression_identifier.as_ref().into();
+                            self.errors.push(AnalyzerError::call_non_function(
+                                &identifier,
+                                &rr.found.kind.to_kind_name(),
+                                self.text,
+                                &token,
+                            ));
                         }
                     }
                 }

crates/analyzer/src/handlers/check_type.rs

@@ -245,14 +245,34 @@ impl<'a> VerylGrammarTrait for CheckType<'a> {
                 let mut params = vec![];
                 let mut ports = vec![];
                 let mut check_port_connection = false;
-                match symbol.found.kind {
+
+                let type_expected = match symbol.found.kind {
                     SymbolKind::Module(ref x) if self.in_module => {
                         params.append(&mut x.parameters.clone());
                         ports.append(&mut x.ports.clone());
                         check_port_connection = true;
+                        None
+                    }
+                    SymbolKind::Interface(_) | SymbolKind::SystemVerilog => None,
+                    SymbolKind::GenericInstance(ref x) => {
+                        let base = symbol_table::get(x.base).unwrap();
+                        match base.kind {
+                            SymbolKind::Module(ref x) if self.in_module => {
+                                params.append(&mut x.parameters.clone());
+                                ports.append(&mut x.ports.clone());
+                                check_port_connection = true;
+                                None
+                            }
+                            SymbolKind::Interface(_) | SymbolKind::SystemVerilog => None,
+                            _ => {
+                                if self.in_module {
+                                    Some("module or interface")
+                                } else {
+                                    Some("interface")
+                                }
+                            }
+                        }
                     }
-                    SymbolKind::Interface(_) => (),
-                    SymbolKind::SystemVerilog => (),
                     SymbolKind::GenericParameter(ref x) => {
                         if let GenericBoundKind::Proto(ref x) = x.bound {
                             if let Ok(symbol) = symbol_table::resolve((x, &symbol.found.namespace))
@@ -261,32 +281,34 @@ impl<'a> VerylGrammarTrait for CheckType<'a> {
                                     params.append(&mut x.parameters.clone());
                                     ports.append(&mut x.ports.clone());
                                     check_port_connection = true;
+                                    None
                                 } else {
-                                    self.errors.push(AnalyzerError::mismatch_type(
-                                        name,
-                                        "module or interface",
-                                        &symbol.found.kind.to_kind_name(),
-                                        self.text,
-                                        &arg.identifier.as_ref().into(),
-                                    ));
+                                    Some("module or interface")
                                 }
+                            } else {
+                                None
                             }
+                        } else {
+                            None
                         }
                     }
                     _ => {
-                        let expected = if self.in_module {
-                            "module or interface"
+                        if self.in_module {
+                            Some("module or interface")
                         } else {
-                            "interface"
-                        };
-                        self.errors.push(AnalyzerError::mismatch_type(
-                            name,
-                            expected,
-                            &symbol.found.kind.to_kind_name(),
-                            self.text,
-                            &arg.identifier.as_ref().into(),
-                        ));
+                            Some("interface")
+                        }
                     }
+                };
+
+                if let Some(expected) = type_expected {
+                    self.errors.push(AnalyzerError::mismatch_type(
+                        name,
+                        expected,
+                        &symbol.found.kind.to_kind_name(),
+                        self.text,
+                        &arg.identifier.as_ref().into(),
+                    ));
                 }
 
                 if check_port_connection {