Allow msb for port

crates/analyzer/src/handlers/check_msb_lsb.rs

@@ -72,8 +72,15 @@ impl<'a> VerylGrammarTrait for CheckMsbLsb<'a> {
                     symbol_table::resolve(self.identifier_path.last().unwrap().clone())
                 {
                     let namespace = &x.found.namespace;
-                    if let SymbolKind::Variable(x) = x.found.kind {
-                        let types = trace_type(&x.r#type, namespace);
+
+                    let r#type = match x.found.kind {
+                        SymbolKind::Variable(x) => Some(x.r#type),
+                        SymbolKind::Port(x) => x.r#type,
+                        _ => None,
+                    };
+
+                    if let Some(x) = r#type {
+                        let types = trace_type(&x, namespace);
                         let mut select_dimension = *self.select_dimension.last().unwrap();
 
                         let mut expression = None;

testcases/sv/28_msblsb.sv

@@ -1,4 +1,6 @@
-module veryl_testcase_Module28;
+module veryl_testcase_Module28 (
+    input logic [30-1:0][40-1:0] c
+);
     localparam int unsigned WIDTH0 = 10;
     localparam int unsigned WIDTH1 = 20;
 
@@ -11,5 +13,7 @@ module veryl_testcase_Module28;
     always_comb _x = a[((10) - 1)][((20) - 1):0 + 1];
     logic _y;
     always_comb _y = b[((WIDTH0 + 10) - 1) - 3][((WIDTH1) - 1) + 5:0];
+    logic _z;
+    always_comb _z = c[((30) - 1)][((40) - 1)];
 endmodule
 //# sourceMappingURL=../map/testcases/sv/28_msblsb.sv.map

testcases/veryl/28_msblsb.veryl

@@ -1,4 +1,6 @@
-module Module28 {
+module Module28 (
+    c: input logic<30, 40>,
+) {
     const WIDTH0: u32 = 10;
     const WIDTH1: u32 = 20;
 
@@ -7,4 +9,5 @@ module Module28 {
 
     let _x: logic = a[msb][msb:lsb + 1];
     let _y: logic = b[msb - 3][msb + 5:lsb];
+    let _z: logic = c[msb][msb];
 }