Allow type parameter override

crates/analyzer/src/handlers/check_expression.rs

@@ -16,6 +16,7 @@ pub struct CheckExpression<'a> {
     evaluator: Evaluator,
     call_stack_kind: Vec<FunctionKind>,
     in_inst_declaration: bool,
+    in_inst_parameter: bool,
 }
 
 #[derive(Debug, Clone, Copy, PartialEq)]
@@ -94,6 +95,15 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> {
                         }
                         // instance can be used as factor in inst_declaration
                         SymbolKind::Instance(_) if self.in_inst_declaration => (),
+                        // type can be used as factor in inst_parameter
+                        SymbolKind::TypeDef(_)
+                        | SymbolKind::Struct(_)
+                        | SymbolKind::Enum(_)
+                        | SymbolKind::Union(_)
+                            if self.in_inst_parameter =>
+                        {
+                            ()
+                        }
                         SymbolKind::Module(_)
                         | SymbolKind::ProtoModule(_)
                         | SymbolKind::Interface(_)
@@ -186,4 +196,12 @@ impl<'a> VerylGrammarTrait for CheckExpression<'a> {
         }
         Ok(())
     }
+
+    fn inst_parameter(&mut self, _arg: &InstParameter) -> Result<(), ParolError> {
+        match self.point {
+            HandlerPoint::Before => self.in_inst_parameter = true,
+            HandlerPoint::After => self.in_inst_parameter = false,
+        }
+        Ok(())
+    }
 }

testcases/sv/71_type_parameter.sv

@@ -0,0 +1,20 @@
+module veryl_testcase_Module71 #(
+    parameter type param_type = logic
+);
+    typedef logic [32-1:0] type_type;
+
+    typedef struct packed {
+        logic a;
+    } struct_type;
+
+    veryl_testcase_Module71A #(.T1 (param_type), .T2 (type_type), .T3 (struct_type) /*T4: logic,*/) m ();
+endmodule
+
+module veryl_testcase_Module71A #(
+    parameter type T1 = logic,
+    parameter type T2 = logic,
+    parameter type T3 = logic,
+    parameter type T4 = logic
+);
+endmodule
+//# sourceMappingURL=../map/testcases/sv/71_type_parameter.sv.map

testcases/veryl/71_type_parameter.veryl

@@ -0,0 +1,18 @@
+module Module71 #(
+    param param_type: type = logic,
+) {
+    type type_type = logic<32>;
+
+    struct struct_type {
+        a: logic,
+    }
+
+    inst m: Module71A #(T1: param_type, T2: type_type, T3: struct_type, /*T4: logic,*/);
+}
+
+module Module71A #(
+    param T1: type = logic,
+    param T2: type = logic,
+    param T3: type = logic,
+    param T4: type = logic,
+) {}