Merge pull request #881 from veryl-lang/suppress_unused_generics

Suppress to emit unused generics
veryl-lang · Aug 13, 2024 · b61173a · b61173a
2 parents 884d139 + e9bbbc8
commit b61173a
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Showing 3 changed files with 18 additions and 1 deletion.
diff --git a/crates/analyzer/src/symbol.rs b/crates/analyzer/src/symbol.rs
@@ -162,7 +162,7 @@ impl Symbol {
         }
 
         // empty map for non-generic
-        if ret.is_empty() {
+        if ret.is_empty() && !self.kind.is_generic() {
             ret.push(GenericMap::default());
         }
         ret
@@ -307,6 +307,18 @@ impl SymbolKind {
             SymbolKind::ClockDomain => "clock domain".to_string(),
         }
     }
+
+    pub fn is_generic(&self) -> bool {
+        match self {
+            SymbolKind::Module(x) => !x.generic_parameters.is_empty(),
+            SymbolKind::Interface(x) => !x.generic_parameters.is_empty(),
+            SymbolKind::Function(x) => !x.generic_parameters.is_empty(),
+            SymbolKind::Package(x) => !x.generic_parameters.is_empty(),
+            SymbolKind::Struct(x) => !x.generic_parameters.is_empty(),
+            SymbolKind::Union(x) => !x.generic_parameters.is_empty(),
+            _ => false,
+        }
+    }
 }
 
 impl fmt::Display for SymbolKind {

diff --git a/testcases/sv/55_generic_module.sv b/testcases/sv/55_generic_module.sv
@@ -39,4 +39,5 @@ endmodule
 module veryl_testcase___Module55F__Module55B;
     veryl_testcase_Module55B u ();
 endmodule
+
 //# sourceMappingURL=../map/testcases/sv/55_generic_module.sv.map
diff --git a/testcases/veryl/55_generic_module.veryl b/testcases/veryl/55_generic_module.veryl
@@ -24,3 +24,7 @@ module Module55E::<T> {
 module Module55F::<T = Module55B> {
     inst u: T;
 }
+
+module Module55G::<T> {
+    inst u: T;
+}