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Allow type with generic parameter as generic argument
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dalance committed Oct 3, 2024
1 parent 519a526 commit c9c433a
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Showing 4 changed files with 41 additions and 5 deletions.
25 changes: 21 additions & 4 deletions crates/analyzer/src/handlers/check_type.rs
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,8 @@ pub struct CheckType<'a> {
text: &'a str,
point: HandlerPoint,
in_module: bool,
in_variable_type: bool,
in_variable_type: Vec<()>,
in_generic_argument: Vec<()>,
in_modport: bool,
}

Expand Down Expand Up @@ -56,8 +57,24 @@ fn is_variable_type(symbol: &Symbol) -> bool {
impl<'a> VerylGrammarTrait for CheckType<'a> {
fn variable_type(&mut self, _arg: &VariableType) -> Result<(), ParolError> {
match self.point {
HandlerPoint::Before => self.in_variable_type = true,
HandlerPoint::After => self.in_variable_type = false,
HandlerPoint::Before => {
self.in_variable_type.push(());
}
HandlerPoint::After => {
self.in_variable_type.pop();
}
}
Ok(())
}

fn with_generic_argument(&mut self, _arg: &WithGenericArgument) -> Result<(), ParolError> {
match self.point {
HandlerPoint::Before => {
self.in_generic_argument.push(());
}
HandlerPoint::After => {
self.in_generic_argument.pop();
}
}
Ok(())
}
Expand All @@ -82,7 +99,7 @@ impl<'a> VerylGrammarTrait for CheckType<'a> {
fn scoped_identifier(&mut self, arg: &ScopedIdentifier) -> Result<(), ParolError> {
if let HandlerPoint::Before = self.point {
// Check variable type
if self.in_variable_type {
if !self.in_variable_type.is_empty() && self.in_generic_argument.is_empty() {
if let Ok(symbol) = symbol_table::resolve(arg) {
if self.in_modport {
if !matches!(symbol.found.kind, SymbolKind::Modport(_)) {
Expand Down
2 changes: 1 addition & 1 deletion testcases/map/testcases/sv/55_generic_module.sv.map

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10 changes: 10 additions & 0 deletions testcases/sv/55_generic_module.sv
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ module veryl_testcase_Module55;
veryl_testcase___Module55E__Module55D u3 ();
veryl_testcase___Module55F__Module55C u4 ();
veryl_testcase___Module55F__Module55B u5 ();
veryl_testcase___Module55H__10 u6 ();
endmodule


Expand Down Expand Up @@ -41,4 +42,13 @@ module veryl_testcase___Module55F__Module55B;
veryl_testcase_Module55B u ();
endmodule


module veryl_testcase___Module55H__10;
typedef struct packed {
logic [10-1:0] value;
} __StructH__10;

__StructH__10 _a;
always_comb _a = 0;
endmodule
//# sourceMappingURL=../map/testcases/sv/55_generic_module.sv.map
9 changes: 9 additions & 0 deletions testcases/veryl/55_generic_module.veryl
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@ module Module55 {
inst u3: Module55E::<Module55D>;
inst u4: Module55F::<Module55C>;
inst u5: Module55F::<>;
inst u6: Module55H::<10>;
}

pub proto module Proto55;
Expand All @@ -31,3 +32,11 @@ module Module55F::<T: Proto55 = Module55B> {
module Module55G::<T: Proto55> {
inst u: T;
}

module Module55H::<W: const> {
struct StructH::<W: const> {
value: logic<W>,
}

let _a: StructH::<W> = 0;
}

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