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signed / unsigned representation #85

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dalance opened this issue Jan 16, 2023 · 2 comments
Closed

signed / unsigned representation #85

dalance opened this issue Jan 16, 2023 · 2 comments
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lang Language design

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@dalance
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dalance commented Jan 16, 2023

Signed / unsigned specifier is not implemented.

signed / unsigned like SV

var a: signed logic[10];
var b: unsigned logic[10];
var c: logic[10]; // signed or unsigned ?

Some problems.

  • bit long
  • word length is not uniformed
  • omitted case may be confusable

ilogic / ulogic

This is the same as isize / usize in Rust.

var a: ilogic[10]; // signed logic in SV
var b: ulogic[10]; // unsigned logic in SV
var c: ibit  [10]; // signed bit in SV
var d: ubit  [10]; // unsigned bit in SV

This seems to be better than signed / unsigned?

@dalance dalance added the lang Language design label Jan 16, 2023
@taichi-ishitani
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I think using a signed value is a special case than using a unsigned value.
Therefore, I prefer introducing the signed keyword as a type modifier like the tri keyword.

@dalance
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dalance commented Jan 17, 2023

OK. It seems to be good that unsigned by default and signed is added only.

dalance added a commit that referenced this issue Jan 17, 2023
@dalance dalance closed this as completed Jan 17, 2023
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