Integer Calculator

Simple RTL Design for Integer Number Calculation in Altera Family and other compatible FPGAs using VHDL.

Guide

Make new Project in Quartus Prime Software.
Generate 32x8 bits single-port RAM.
Create 7 Segment Entity for Output.
Create each Arithmatical operation entity ( this project will only covers addition, substraction, division, multiplication, factorial, square, volume, and square root operation ).
Combine All Entity into one main Entity.

For documentation, check in the documentation folder that are provided in this repository.

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
documentation		documentation
Decimal_Adder.vhd		Decimal_Adder.vhd
Decimal_Divider.vhd		Decimal_Divider.vhd
Decimal_Factorial.vhd		Decimal_Factorial.vhd
Decimal_Multiplier.vhd		Decimal_Multiplier.vhd
Decimal_Square.vhd		Decimal_Square.vhd
Decimal_Substractor.vhd		Decimal_Substractor.vhd
Decimal_Volume.vhd		Decimal_Volume.vhd
LICENSE		LICENSE
Memblock_Calc.vhd		Memblock_Calc.vhd
README.md		README.md
Squart.vhd		Squart.vhd
_config.yml		_config.yml
ram32x8.vhd		ram32x8.vhd
seven_segment.vhd		seven_segment.vhd