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Initial Patch for RISC-V support #82294

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da21fa4
[WIP] RISCV64 REL BUILD
clamp03 Oct 26, 2022
9ff3bdc
[WIP] RISCV64 DBG BUILD
clamp03 Nov 8, 2022
499e598
[WIP] FIX
clamp03 Nov 8, 2022
7433745
[WIP] FIX WHAT I DID FOR THREAD STORE TEST
clamp03 Nov 10, 2022
7587b73
[WIP] UPDATE ASSEMBLY FUNCTIONS and ADD CRASH TO UNIMPLEMENTED
clamp03 Nov 10, 2022
c7bd561
[WIP] UPDATE CRTHELPERS
clamp03 Nov 10, 2022
4ca0934
[WIP] UPDATE EXCEPTIONHANDLER AND CALLDESCRWORKERRISCV64
clamp03 Nov 10, 2022
8bdde90
[WIP] UPDATE ACTIVATIONHANDLERWRAPPER
clamp03 Nov 10, 2022
260fdc4
[WIP] CALLSIGNALHANDLEWRAPPER
clamp03 Nov 10, 2022
de1c03e
[WIP] FLOATCONVERSION, DBGHELPERS
clamp03 Nov 10, 2022
1a45b75
[WIP] PAL, ASMCONSTANTS, CONTEXT2
clamp03 Nov 11, 2022
da10fc8
[WIP] REMOVE ACTIVATIONHANDLERWRAPPER, DISPATCHEXCEPTIONWRAPPER
clamp03 Nov 11, 2022
0cb6eb6
[WIP] ADD CRASH INSTRS FOR UNINPLEMENTED
clamp03 Nov 11, 2022
896a978
[WIP] ASMHELPERS
clamp03 Nov 14, 2022
7c9508c
[WIP] PINVOKESTUBS
clamp03 Nov 14, 2022
f6e85fa
[WIP] RESTORE getcontext.S and setcontext.S in libunwind
clamp03 Nov 14, 2022
4c12c26
[WIP] FIX THREADS.CPP
clamp03 Nov 15, 2022
f5e184d
[WIP] FIX PRECODE
clamp03 Nov 15, 2022
df30a97
[WIP] SET REG
clamp03 Nov 15, 2022
322c2b9
[WIP] FIX INTERPRETER
clamp03 Nov 21, 2022
1120e51
[WIP] Revert Interpreter Code Changes
clamp03 Nov 24, 2022
93d30e7
[WIP] JIT
clamp03 Nov 24, 2022
47938e6
[WIP] JIT
clamp03 Nov 25, 2022
a01b735
[WIP] JIT
clamp03 Nov 30, 2022
7bf58ed
[WIP] JIT
clamp03 Dec 1, 2022
da5220a
[WIP] JIT
clamp03 Dec 2, 2022
c7063e9
[WIP] JIT
clamp03 Dec 5, 2022
55a83da
[WIP] JIT
clamp03 Dec 5, 2022
894ac25
[WIP] JIT
clamp03 Dec 6, 2022
a5d54c3
[WIP] JIT
clamp03 Dec 7, 2022
6377887
[WIP] JIT
clamp03 Dec 9, 2022
95119c7
[WIP] JIT
clamp03 Dec 19, 2022
eb939c1
[WIP] JIT
clamp03 Dec 20, 2022
c241e32
[WIP] JIT
clamp03 Dec 20, 2022
0893b92
[WIP] JIT
clamp03 Dec 20, 2022
a03513a
[WIP] JIT
clamp03 Dec 21, 2022
e714c1a
[WIP] JIT
clamp03 Dec 22, 2022
dfde411
[WIP] JIT
clamp03 Dec 22, 2022
3683323
[WIP] JIT
clamp03 Dec 23, 2022
733a4d5
[WIP] JIT
clamp03 Dec 26, 2022
18c37ce
[WIP] JIT
clamp03 Dec 27, 2022
ade1a59
[WIP] JIT
clamp03 Dec 29, 2022
b3cf2ae
[WIP] JIT
clamp03 Dec 29, 2022
589f6a3
[WIP] JIT
clamp03 Jan 2, 2023
8f91e27
[WIP] JIT
clamp03 Jan 2, 2023
6882d87
[WIP] FIX JIT ERRORS
clamp03 Jan 3, 2023
ca1ad78
[WIP] FIX PROLOG REGISTER SAVES
clamp03 Jan 3, 2023
29699c1
[WIP] FIX and UPDATE JIT
clamp03 Jan 3, 2023
54f892b
[WIP] IMPLEMENTS SHIFT, ROTATE, NEG, NOT and FENCE
clamp03 Jan 3, 2023
558f214
[WIP] JIT UPDATE
clamp03 Jan 4, 2023
bc14f0a
[WIP] FIX DISP
clamp03 Jan 5, 2023
d8fe5ca
[WIP] JIT DEBUGGING
clamp03 Jan 5, 2023
4bc1b27
[WIP] JIT
clamp03 Jan 9, 2023
e1da0a6
[WIP] JIT
clamp03 Jan 10, 2023
b5f8bd5
[WIP] JIT
clamp03 Jan 11, 2023
f23ef1b
[WIP] JIT
clamp03 Jan 11, 2023
3fbfff1
[WIP] FIX JIT
clamp03 Jan 12, 2023
6b64b3d
[WIP] JIT
clamp03 Jan 12, 2023
52aafd2
[WIP] JIT
clamp03 Jan 12, 2023
eea327c
[WIP] JIT
clamp03 Jan 13, 2023
81fe2a0
[WIP] JIT
clamp03 Jan 13, 2023
13650ae
[WIP] JIT
clamp03 Jan 13, 2023
e753f43
[WIP] JIT
clamp03 Jan 16, 2023
d44f9ec
[WIP] JIT
clamp03 Jan 16, 2023
a601385
[WIP] JIT
clamp03 Jan 17, 2023
12ccf4f
[WIP] JIT
clamp03 Jan 17, 2023
8a87d86
[WIP] JIT
clamp03 Jan 18, 2023
c00a4cd
[WIP] JIT
clamp03 Jan 18, 2023
57df5a9
[WIP] JIT
clamp03 Jan 19, 2023
0db2c5c
[WIP] JIT
clamp03 Jan 19, 2023
be097ae
[WIP] JIT
clamp03 Jan 19, 2023
5f2eb7b
[WIP] JIT
clamp03 Jan 20, 2023
e9b852e
[WIP] JIT
clamp03 Jan 20, 2023
4709724
[WIP] JIT
clamp03 Jan 20, 2023
c58aee1
[WIP] JIT
clamp03 Jan 20, 2023
498276f
[WIP] JIT
clamp03 Jan 20, 2023
5cae87a
[WIP] JIT
clamp03 Jan 30, 2023
af66496
[WIP] JIT
clamp03 Jan 31, 2023
a6791ed
[WIP] JIT
clamp03 Feb 1, 2023
15b448e
[WIP] JIT
clamp03 Feb 1, 2023
407e25d
[WIP] JIT
clamp03 Feb 1, 2023
2b3b528
[WIP] JIT
clamp03 Feb 2, 2023
5638069
[WIP] JIT
clamp03 Feb 2, 2023
9641baf
[WIP] JIT
clamp03 Feb 3, 2023
5070785
[WIP] JIT
clamp03 Feb 3, 2023
553c1fd
[WIP] JIT
clamp03 Feb 7, 2023
e7a0474
[WIP] TESTS
clamp03 Feb 13, 2023
e147059
[WIP] JIT
clamp03 Feb 13, 2023
91ce589
[WIP] PALTEST
clamp03 Feb 15, 2023
0827ede
[WIP] FIX AFTER REBASE
clamp03 Feb 17, 2023
6b81f2d
[WIP] Remove commented codes
clamp03 Feb 17, 2023
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12 changes: 8 additions & 4 deletions src/coreclr/clrdefinitions.cmake
Original file line number Diff line number Diff line change
Expand Up @@ -197,12 +197,12 @@ if (CLR_CMAKE_TARGET_ARCH_AMD64)
add_definitions(-DUNIX_AMD64_ABI_ITF)
endif (CLR_CMAKE_TARGET_ARCH_AMD64)
add_definitions(-DFEATURE_USE_ASM_GC_WRITE_BARRIERS)
if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
add_definitions(-DFEATURE_USE_SOFTWARE_WRITE_WATCH_FOR_GC_HEAP)
endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
add_definitions(-DFEATURE_MANUALLY_MANAGED_CARD_BUNDLES)
endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
endif(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)

if(NOT CLR_CMAKE_TARGET_UNIX)
add_definitions(-DFEATURE_WIN32_REGISTRY)
Expand Down Expand Up @@ -275,6 +275,10 @@ function(set_target_definitions_to_custom_os_and_arch)
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_MULTIREG_RETURN)
elseif((TARGETDETAILS_ARCH STREQUAL "arm") OR (TARGETDETAILS_ARCH STREQUAL "armel"))
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE TARGET_ARM)
elseif((TARGETDETAILS_ARCH STREQUAL "riscv64"))
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE TARGET_64BIT)
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE TARGET_RISCV64)
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_MULTIREG_RETURN)
endif()

if (TARGETDETAILS_ARCH STREQUAL "armel")
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/debug/createdump/createdumpunix.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

#include "createdump.h"

#if defined(__arm__) || defined(__aarch64__) || defined(__loongarch64)
#if defined(__arm__) || defined(__aarch64__) || defined(__loongarch64) || defined(__riscv)
long g_pageSize = 0;
#endif

Expand All @@ -19,7 +19,7 @@ CreateDump(const char* dumpPathTemplate, int pid, const char* dumpType, MINIDUMP
bool result = false;

// Initialize PAGE_SIZE
#if defined(__arm__) || defined(__aarch64__) || defined(__loongarch64)
#if defined(__arm__) || defined(__aarch64__) || defined(__loongarch64) || defined(__riscv)
g_pageSize = sysconf(_SC_PAGESIZE);
#endif
TRACE("PAGE_SIZE %d\n", PAGE_SIZE);
Expand Down
4 changes: 3 additions & 1 deletion src/coreclr/debug/createdump/datatarget.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,8 @@ DumpDataTarget::GetMachineType(
*machine = IMAGE_FILE_MACHINE_I386;
#elif HOST_LOONGARCH64
*machine = IMAGE_FILE_MACHINE_LOONGARCH64;
#elif HOST_RISCV64
*machine = IMAGE_FILE_MACHINE_RISCV64;
#else
#error Unsupported architecture
#endif
Expand All @@ -87,7 +89,7 @@ HRESULT STDMETHODCALLTYPE
DumpDataTarget::GetPointerSize(
/* [out] */ ULONG32 *size)
{
#if defined(HOST_AMD64) || defined(HOST_ARM64) || defined(HOST_LOONGARCH64)
#if defined(HOST_AMD64) || defined(HOST_ARM64) || defined(HOST_LOONGARCH64) || defined(HOST_RISCV64)
*size = 8;
#elif defined(HOST_ARM) || defined(HOST_X86)
*size = 4;
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/debug/createdump/dumpwriterelf.h
Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,8 @@
#define ELF_ARCH EM_ARM
#elif defined(__loongarch64)
#define ELF_ARCH EM_LOONGARCH
#elif defined(__riscv)
#define ELF_ARCH EM_RISCV
#endif

#define PH_HDR_CANARY 0xFFFF
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/debug/createdump/memoryregion.h
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.

#if !defined(PAGE_SIZE) && (defined(__arm__) || defined(__aarch64__) || defined(__loongarch64))
#if !defined(PAGE_SIZE) && (defined(__arm__) || defined(__aarch64__) || defined(__loongarch64)) || defined(__riscv)
extern long g_pageSize;
#define PAGE_SIZE g_pageSize
#endif
Expand Down
18 changes: 18 additions & 0 deletions src/coreclr/debug/createdump/threadinfo.h
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,14 @@ class CrashInfo;
#define MCREG_Pc(mc) ((mc).pc)
#endif

#if defined(__riscv)
// See src/coreclr/pal/src/include/pal/context.h
#define MCREG_Ra(mc) ((mc).ra)
#define MCREG_Fp(mc) ((mc).s0)
#define MCREG_Sp(mc) ((mc).sp)
#define MCREG_Pc(mc) ((mc).pc)
#endif

#define FPREG_ErrorOffset(fpregs) *(DWORD*)&((fpregs).rip)
#define FPREG_ErrorSelector(fpregs) *(((WORD*)&((fpregs).rip)) + 2)
#define FPREG_DataOffset(fpregs) *(DWORD*)&((fpregs).rdp)
Expand All @@ -30,6 +38,12 @@ class CrashInfo;
#elif defined(__loongarch64)
// struct user_regs_struct {} defined `/usr/include/loongarch64-linux-gnu/sys/user.h`

struct user_fpregs_struct
{
unsigned long long fpregs[32];
unsigned long fpscr;
} __attribute__((__packed__));
#elif defined(__riscv)
struct user_fpregs_struct
{
unsigned long long fpregs[32];
Expand Down Expand Up @@ -154,6 +168,10 @@ class ThreadInfo
inline const uint64_t GetInstructionPointer() const { return m_gpRegisters.ARM_pc; }
inline const uint64_t GetStackPointer() const { return m_gpRegisters.ARM_sp; }
inline const uint64_t GetFramePointer() const { return m_gpRegisters.ARM_fp; }
#elif defined(__riscv)
inline const uint64_t GetInstructionPointer() const { return MCREG_Pc(m_gpRegisters); }
inline const uint64_t GetStackPointer() const { return MCREG_Sp(m_gpRegisters); }
inline const uint64_t GetFramePointer() const { return MCREG_Fp(m_gpRegisters); }
#endif
#endif // __APPLE__

Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/debug/createdump/threadinfounix.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -59,6 +59,8 @@ ThreadInfo::Initialize()
TRACE("Thread %04x RIP %016llx RSP %016llx\n", m_tid, (unsigned long long)m_gpRegisters.rip, (unsigned long long)m_gpRegisters.rsp);
#elif defined(__loongarch64)
TRACE("Thread %04x PC %016llx SP %016llx\n", m_tid, (unsigned long long)m_gpRegisters.pc, (unsigned long long)m_gpRegisters.gpr[3]);
#elif defined(__riscv)
TRACE("Thread %04x PC %016llx SP %016llx\n", m_tid, (unsigned long long)m_gpRegisters.pc, (unsigned long long)m_gpRegisters.sp);
#else
#error "Unsupported architecture"
#endif
Expand Down Expand Up @@ -243,6 +245,8 @@ ThreadInfo::GetThreadContext(uint32_t flags, CONTEXT* context) const
memcpy(context->F, m_fpRegisters.fpregs, sizeof(context->F));
context->Fcsr = m_fpRegisters.fpscr;
}
#elif defined(__riscv)
_ASSERTE(!"TODO RISCV64 NYI");
#else
#error Platform not supported
#endif
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/debug/daccess/daccess.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5446,6 +5446,8 @@ ClrDataAccess::Initialize(void)
CorDebugPlatform hostPlatform = CORDB_PLATFORM_POSIX_ARM64;
#elif defined(TARGET_LOONGARCH64)
CorDebugPlatform hostPlatform = CORDB_PLATFORM_POSIX_LOONGARCH64;
#elif defined(TARGET_RISCV64)
CorDebugPlatform hostPlatform = CORDB_PLATFORM_POSIX_RISCV64;
#else
#error Unknown Processor.
#endif
Expand Down
12 changes: 12 additions & 0 deletions src/coreclr/debug/daccess/request.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -559,6 +559,18 @@ ClrDataAccess::GetRegisterName(int regNum, unsigned int count, _Inout_updates_z_
W("S6"), W("S7"), W("K0"), W("K1"),
W("GP"), W("SP"), W("FP"), W("RA")
};
#elif defined(TARGET_RISCV64)
static const WCHAR *regs[] =
{
W("R0"), W("RA"), W("SP"), W("GP"),
W("TP"), W("T0"), W("T1"), W("T2"),
W("FP"), W("S1"), W("A0"), W("A1"),
W("A2"), W("A3"), W("A4"), W("A5"),
W("A6"), W("A7"), W("S2"), W("S3"),
W("S4"), W("S5"), W("S6"), W("S7"),
W("S8"), W("S9"), W("S10"), W("S11"),
W("T3"), W("T4"), W("T5"), W("T6")
};
#endif

// Caller frame registers are encoded as "-(reg+1)".
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/debug/di/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -66,7 +66,7 @@ if(CLR_CMAKE_HOST_WIN32)
endif()
elseif(CLR_CMAKE_HOST_UNIX)

if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_ARM OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64)
if(CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_ARM OR CLR_CMAKE_TARGET_ARCH_LOONGARCH64 OR CLR_CMAKE_TARGET_ARCH_RISCV64)
set(CORDBDI_SOURCES_ASM_FILE
${ARCH_SOURCES_DIR}/floatconversion.S
)
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/debug/di/module.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4872,6 +4872,8 @@ int CordbNativeCode::GetCallInstructionLength(BYTE *ip, ULONG32 count)

_ASSERTE(!"Invalid opcode!");
return -1;
#elif defined(TARGET_RISCV64)
return MAX_INSTRUCTION_LENGTH;
#else
#error Platform not implemented
#endif
Expand Down
3 changes: 3 additions & 0 deletions src/coreclr/debug/di/platformspecific.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,9 @@
#elif TARGET_LOONGARCH64
#include "loongarch64/cordbregisterset.cpp"
#include "loongarch64/primitives.cpp"
#elif TARGET_RISCV64
#include "riscv64/cordbregisterset.cpp"
#include "riscv64/primitives.cpp"
#else
#error Unsupported platform
#endif
116 changes: 116 additions & 0 deletions src/coreclr/debug/di/riscv64/cordbregisterset.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,116 @@
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.

//*****************************************************************************
// File: CordbRegisterSet.cpp
//

//
//*****************************************************************************
#include "primitives.h"


HRESULT CordbRegisterSet::GetRegistersAvailable(ULONG64* pAvailable)
{
FAIL_IF_NEUTERED(this);
VALIDATE_POINTER_TO_OBJECT(pAvailable, ULONG64 *);

*pAvailable = SETBITULONG64(REGISTER_RISCV64_PC)
| SETBITULONG64(REGISTER_RISCV64_RA)
| SETBITULONG64(REGISTER_RISCV64_SP)
| SETBITULONG64(REGISTER_RISCV64_GP)
| SETBITULONG64(REGISTER_RISCV64_TP)
| SETBITULONG64(REGISTER_RISCV64_T0)
| SETBITULONG64(REGISTER_RISCV64_T1)
| SETBITULONG64(REGISTER_RISCV64_T2)
| SETBITULONG64(REGISTER_RISCV64_FP)
| SETBITULONG64(REGISTER_RISCV64_S1)
| SETBITULONG64(REGISTER_RISCV64_A0)
| SETBITULONG64(REGISTER_RISCV64_A1)
| SETBITULONG64(REGISTER_RISCV64_A2)
| SETBITULONG64(REGISTER_RISCV64_A3)
| SETBITULONG64(REGISTER_RISCV64_A4)
| SETBITULONG64(REGISTER_RISCV64_A5)
| SETBITULONG64(REGISTER_RISCV64_A6)
| SETBITULONG64(REGISTER_RISCV64_A7)
| SETBITULONG64(REGISTER_RISCV64_S2)
| SETBITULONG64(REGISTER_RISCV64_S3)
| SETBITULONG64(REGISTER_RISCV64_S4)
| SETBITULONG64(REGISTER_RISCV64_S5)
| SETBITULONG64(REGISTER_RISCV64_S6)
| SETBITULONG64(REGISTER_RISCV64_S7)
| SETBITULONG64(REGISTER_RISCV64_S8)
| SETBITULONG64(REGISTER_RISCV64_S9)
| SETBITULONG64(REGISTER_RISCV64_S10)
| SETBITULONG64(REGISTER_RISCV64_S11)
| SETBITULONG64(REGISTER_RISCV64_T3)
| SETBITULONG64(REGISTER_RISCV64_T4)
| SETBITULONG64(REGISTER_RISCV64_T5)
| SETBITULONG64(REGISTER_RISCV64_T6)
| SETBITULONG64(REGISTER_RISCV64_F0)
| SETBITULONG64(REGISTER_RISCV64_F1)
| SETBITULONG64(REGISTER_RISCV64_F2)
| SETBITULONG64(REGISTER_RISCV64_F3)
| SETBITULONG64(REGISTER_RISCV64_F4)
| SETBITULONG64(REGISTER_RISCV64_F5)
| SETBITULONG64(REGISTER_RISCV64_F6)
| SETBITULONG64(REGISTER_RISCV64_F7)
| SETBITULONG64(REGISTER_RISCV64_F8)
| SETBITULONG64(REGISTER_RISCV64_F9)
| SETBITULONG64(REGISTER_RISCV64_F10)
| SETBITULONG64(REGISTER_RISCV64_F11)
| SETBITULONG64(REGISTER_RISCV64_F12)
| SETBITULONG64(REGISTER_RISCV64_F13)
| SETBITULONG64(REGISTER_RISCV64_F14)
| SETBITULONG64(REGISTER_RISCV64_F15)
| SETBITULONG64(REGISTER_RISCV64_F16)
| SETBITULONG64(REGISTER_RISCV64_F17)
| SETBITULONG64(REGISTER_RISCV64_F18)
| SETBITULONG64(REGISTER_RISCV64_F19)
| SETBITULONG64(REGISTER_RISCV64_F20)
| SETBITULONG64(REGISTER_RISCV64_F21)
| SETBITULONG64(REGISTER_RISCV64_F22)
| SETBITULONG64(REGISTER_RISCV64_F23)
| SETBITULONG64(REGISTER_RISCV64_F24)
| SETBITULONG64(REGISTER_RISCV64_F25)
| SETBITULONG64(REGISTER_RISCV64_F26)
| SETBITULONG64(REGISTER_RISCV64_F27)
| SETBITULONG64(REGISTER_RISCV64_F28)
| SETBITULONG64(REGISTER_RISCV64_F29)
| SETBITULONG64(REGISTER_RISCV64_F30)
| SETBITULONG64(REGISTER_RISCV64_F31);

return S_OK;
}

HRESULT CordbRegisterSet::GetRegisters(ULONG64 mask, ULONG32 regCount,
CORDB_REGISTER regBuffer[])
{
_ASSERTE(!"RISCV64:NYI");
return S_OK;
}


HRESULT CordbRegisterSet::GetRegistersAvailable(ULONG32 regCount,
BYTE pAvailable[])
{
_ASSERTE(!"RISCV64:NYI");
return S_OK;
}


HRESULT CordbRegisterSet::GetRegisters(ULONG32 maskCount, BYTE mask[],
ULONG32 regCount, CORDB_REGISTER regBuffer[])
{
_ASSERTE(!"RISCV64:NYI");
return S_OK;
}


// This is just a convenience function to convert a regdisplay into a Context.
// Since a context has more info than a regdisplay, the conversion isn't perfect
// and the context can't be fully accurate.
void CordbRegisterSet::InternalCopyRDToContext(DT_CONTEXT *pInputContext)
{
_ASSERTE(!"RISCV64:NYI");
}
12 changes: 12 additions & 0 deletions src/coreclr/debug/di/riscv64/floatconversion.S
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.

#include <unixasmmacros.inc>

// Arguments
// input: (in A0) the value to be converted to a double
// output: the double corresponding to the _NEON128 input value
LEAF_ENTRY FPFillR8, .TEXT
ld a0, 0(a0)
jalr x0, ra, 0
LEAF_END FPFillR8, .TEXT
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.

#include "unixasmmacros.inc"
#include "asmconstants.h"
//

#error "TODO-RISCV64: missing implementation"
#include "../../shared/riscv64/primitives.cpp"
7 changes: 7 additions & 0 deletions src/coreclr/debug/di/rsthread.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -8331,6 +8331,9 @@ HRESULT CordbJITILFrame::GetNativeVariable(CordbType *type,
#elif defined(TARGET_LOONGARCH64)
hr = m_nativeFrame->GetLocalFloatingPointValue(pNativeVarInfo->loc.vlReg.vlrReg + REGISTER_LOONGARCH64_F0,
type, ppValue);
#elif defined(TARGET_RISCV64)
hr = m_nativeFrame->GetLocalFloatingPointValue(pNativeVarInfo->loc.vlReg.vlrReg + REGISTER_RISCV64_F0,
type, ppValue);
#else
#error Platform not implemented
#endif // TARGET_ARM @ARMTODO
Expand Down Expand Up @@ -8769,6 +8772,8 @@ HRESULT CordbJITILFrame::GetReturnValueForType(CordbType *pType, ICorDebugValue
const CorDebugRegister floatRegister = REGISTER_ARM_D0;
#elif defined(TARGET_LOONGARCH64)
const CorDebugRegister floatRegister = REGISTER_LOONGARCH64_F0;
#elif defined(TARGET_RISCV64)
const CorDebugRegister floatRegister = REGISTER_RISCV64_F0;
#endif

#if defined(TARGET_X86)
Expand All @@ -8783,6 +8788,8 @@ HRESULT CordbJITILFrame::GetReturnValueForType(CordbType *pType, ICorDebugValue
const CorDebugRegister ptrHighWordRegister = REGISTER_ARM_R1;
#elif defined(TARGET_LOONGARCH64)
const CorDebugRegister ptrRegister = REGISTER_LOONGARCH64_A0;
#elif defined(TARGET_RISCV64)
const CorDebugRegister ptrRegister = REGISTER_RISCV64_A0;
#endif

CorElementType corReturnType = pType->GetElementType();
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/debug/di/shimremotedatatarget.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -232,6 +232,8 @@ ShimRemoteDataTarget::GetPlatform(
*pPlatform = CORDB_PLATFORM_POSIX_ARM64;
#elif defined(TARGET_LOONGARCH64)
*pPlatform = CORDB_PLATFORM_POSIX_LOONGARCH64;
#elif defined(TARGET_RISCV64)
*pPlatform = CORDB_PLATFORM_POSIX_RISCV64;
#else
#error Unknown Processor.
#endif
Expand Down
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