Odroid-N2: arm64/dts: fix audio model name #394
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Change-Id: I8e3e7707ac182f3956f7415a80876b9d4c8ac771
Add missing static qualifier to the chipid initcall function. Change-Id: I3d0b4b5d7710fe69e23a94637f640dff736f3661 Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
…xynos5 All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable support for them directly in the base dtsi. None of the known firmware properly configures CNTFRQ arch timer register, so force clock frequency to 24MHz, which is the only configuration supported by the remaining clock drivers so far. Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset properly other arch timer registers, so add respective properties indicating that. Other Exynos5-based boards behaves correctly in this area, what finally allows to enable support for KVM-based virtualization. Change-Id: I87807b0bcd63d6d98f9765fd4cb9663ab5d221e9 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
…2.0 PHY PHY calibration is needed only for USB2.0 (UTMI) PHY, so skip calling calibration code when phy_calibrate() is called for USB3.0 (PIPE3) PHY. Fixes: d8c80bb ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800") Change-Id: Ic3aaf6e70648e1a0a8177d3501f64c0ecfff2951 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
Change-Id: Ia3c94b0ee99e761a774ac63398ca86477b703b8c Signed-off-by: Brian Kim <brian.kim@hardkernel.com> Signed-off-by: memeka <mihailescu2m@gmail.com> Signed-off-by: Dongjin Kim <tobetter@gmail.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
…ild EDIDs
- 480x800 60hz
- 848x480 60hz
- 1024x600 60hz (the old one is 1024x600p43hz)
- 1152x864 75hz
- 1280x768 60hz
- 1400x1050 60hz
- 1792x1344 60hz
- 1920x800 60hz
- 1920x1080 24Hz
- 1920x1080 23.976Hz
- 1920x1200 60hz
- support for Vu5A
- support for Vu7A+
new file: firmware/edid/480x800.bin
new file: firmware/edid/640x480.bin
new file: firmware/edid/720x480.bin
new file: firmware/edid/720x576.bin
new file: firmware/edid/800x480.bin
new file: firmware/edid/800x600.bin
new file: firmware/edid/848x480.bin
new file: firmware/edid/1024x600.bin
new file: firmware/edid/1024x768.bin
new file: firmware/edid/1152x864_75hz.bin
new file: firmware/edid/1280x1024.bin
new file: firmware/edid/1280x720.bin
new file: firmware/edid/1280x768.bin
new file: firmware/edid/1280x800.bin
new file: firmware/edid/1360x768.bin
new file: firmware/edid/1366x768.bin
new file: firmware/edid/1400x1050.bin
new file: firmware/edid/1440x900.bin
new file: firmware/edid/1600x1200.bin
new file: firmware/edid/1600x900.bin
new file: firmware/edid/1680x1050.bin
new file: firmware/edid/1792x1344.bin
new file: firmware/edid/1920x1080.bin
new file: firmware/edid/1920x1080_23_976hz.bin
new file: firmware/edid/1920x1080_24hz.bin
new file: firmware/edid/1920x1080_50hz.bin
new file: firmware/edid/1920x1200_30hz.bin
new file: firmware/edid/1920x1200_60hz.bin
new file: firmware/edid/1920x800.bin
To support Vu5A, a pixel clock, 33.9MHz is needed.
But, there is no exact hdmi phy table of exynos5422,
so the cloest table will be used as a workaround.
- Vu5A timing
Detailed mode: Clock 33.900 MHz, 476 mm x 268 mm
800 844 932 1056 hborder 0
480 483 489 535 vborder 0
+hsync +vsync
To support Vu7A+, a pixel clock, 49MHz is needed.
But there is no exact hdmi phy table of exynos5422,
so the closest table of 50.04MHz will be used
as a workaround.
- Vu7A+ timing
Detailed mode (1) : Clock 49 MHz, 255 mm x 255 mm
1024 1029 1042 1312 hborder 0
600 602 605 622 vborder 0
-hsync +vsync
- 1024x600 60hz timing
Detailed mode: Clock 50.400 MHz, 355 mm x 208 mm
1024 1048 1184 1344 hborder 0
600 601 604 625 vborder 0
-hsync +vsync
Change-Id: I1278be0ef8812d709429f02f1738c73033e2d5a0
Signed-off-by: memeka <mihailescu2m@gmail.com>
On Exynos there is a solid color plane that is logically below all the other display planes. This causes display artifacts due to alpha. The patch disables blending the base plane with the solid color plane (no alpha). Change-Id: Ibb2ada1d7a7be156d2f05ed477ee5972d63edd98 Reviewed-by: memeka <mihailescu2m@gmail.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
Change-Id: Ia83449849d4636baf57ed64d7183c2a9cec7fe22 Signed-off-by: memeka <mihailescu2m@gmail.com>
Change-Id: Ida63e217cd989d661b7620d390515c0ffcb830ac Signed-off-by: memeka <mihailescu2m@gmail.com>
…acks This patch moves vb2_dc_get_base_sgt() function above mmap buffers callbacks, particularly vb2_dc_alloc() and vb2_dc_mmap() from where it will be called for cacheable MMAP support introduced in the next patch. Change-Id: Ia504fbc1f0b3741986e8fff1ad329215b6e2db2e Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
DMA allocations for MMAP type are uncached by default. But for some cases, CPU has to access the buffers. ie: memcpy for format converter. Supporting cacheable MMAP improves huge performance. This patch enables cacheable memory for DMA coherent allocator in mmap buffer allocation if non-consistent DMA attribute is set and kernel mapping is present. Even if userspace doesn't mmap the buffer, sync still should be happening if kernel mapping is present. If not done in allocation, it is enabled when memory is mapped from userspace (if non-consistent DMA attribute is set). Change-Id: I1e8e65086a2e4511563e8e7c3748d3b5403f18c3 Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Tested-by: Heng-ruey Hsu <henryhsu@chromium.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
Change-Id: I6b574d2a73ed0cda41e19f1e4982828f8f591177 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
…ormance Change-Id: I2054a87278e545515be927ddcc52f52991224a6e Signed-off-by: memeka <mihailescu2m@gmail.com>
…tput Change-Id: Ic3a2f6eb94d60604df50976eca4e210898f40b32 Signed-off-by: memeka <mihailescu2m@gmail.com>
If streaming is active when the MFC device is closed, it will generate an IOMMU page-fault. Change-Id: Ie5c664ecddaebedf282eae1d56e82821b5883ffd Signed-off-by: memeka <mihailescu2m@gmail.com>
Add new table rate for VPLL for Exynos 542x SoC required to support Mali GPU clock frequencies. Change-Id: I71303661fe2f66840386028ef2a53f2242073eef
…cks on G3D path Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D, so the G3D MALI driver can simply adjust the rate of its clock by doing a single clk_set_rate() call, without the need to know the whole clock topology in Exynos542x SoCs. Change-Id: I0506b4cf9c5318ee8d16a5122a21e0bf8ad20e62 Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
All top clocks on G3D path has to be enabled all the time to allow proper G3D power domain operation. This is achieved by adding CRITICAL flag to "mout_sw_aclk_g3d" clock, what keeps this clock and all its parents enabled. This fixes following imprecise abort issue observed on Odroid XU3/XU4 after enabling Panfrost driver by commit 1a5a85c "ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"): panfrost 11800000.gpu: clock rate = 400000000 panfrost 11800000.gpu: failed to get regulator: -517 panfrost 11800000.gpu: regulator init failed -517 Power domain G3D disable failed ... panfrost 11800000.gpu: clock rate = 400000000 8<--- cut here --- Unhandled fault: imprecise external abort (0x1406) at 0x00000000 pgd = (ptrval) [00000000] *pgd=00000000 Internal error: : 1406 [hardkernel#1] PREEMPT SMP ARM Modules linked in: CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) Workqueue: events deferred_probe_work_func PC is at panfrost_gpu_soft_reset+0x94/0x110 LR is at ___might_sleep+0x128/0x2dc ... [<c05c231c>] (panfrost_gpu_soft_reset) from [<c05c2704>] (panfrost_gpu_init+0x10/0x67c) [<c05c2704>] (panfrost_gpu_init) from [<c05c15d0>] (panfrost_device_init+0x158/0x2cc) [<c05c15d0>] (panfrost_device_init) from [<c05c0cb0>] (panfrost_probe+0x80/0x178) [<c05c0cb0>] (panfrost_probe) from [<c05cfaa0>] (platform_drv_probe+0x48/0x9c) [<c05cfaa0>] (platform_drv_probe) from [<c05cd20c>] (really_probe+0x1c4/0x474) [<c05cd20c>] (really_probe) from [<c05cd694>] (driver_probe_device+0x78/0x1bc) [<c05cd694>] (driver_probe_device) from [<c05cb374>] (bus_for_each_drv+0x74/0xb8) [<c05cb374>] (bus_for_each_drv) from [<c05ccfa8>] (__device_attach+0xd4/0x16c) [<c05ccfa8>] (__device_attach) from [<c05cc110>] (bus_probe_device+0x88/0x90) [<c05cc110>] (bus_probe_device) from [<c05cc634>] (deferred_probe_work_func+0x4c/0xd0) [<c05cc634>] (deferred_probe_work_func) from [<c0149df0>] (process_one_work+0x300/0x864) [<c0149df0>] (process_one_work) from [<c014a3ac>] (worker_thread+0x58/0x5a0) [<c014a3ac>] (worker_thread) from [<c0151174>] (kthread+0x12c/0x160) [<c0151174>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) Exception stack(0xee03dfb0 to 0xee03dff8) ... Code: e594300c e5933020 e3130c01 1a00000f (ebefff50). ---[ end trace badde2b74a65a540 ]--- In the above case, the Panfrost driver disables G3D clocks after failure of getting the needed regulator and return with -EPROVE_DEFER code. This causes G3D power domain disable failure and then, during second probe an imprecise abort is triggered due to undefined power domain state. Fixes: 45f10da ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path") Fixes: c9f7567 ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Change-Id: Ic999b9c06b43a3fa148ab254ccef518cecc99460 Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
… Odroid XU3/4 Add device tree node for Mali GPU for Exynos 542x SoC. GPU is disabled by default, and is enabled for each board after the regulator is defined. Tested on Odroid-XU4. Change-Id: I902932d29c7093b666fa3a8a8e1d0fda8fb11d5c Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>
…422 TMU Change-Id: I6014d6d3fdecb6f58c6160f79ac969c6816f365d Signed-off-by: memeka <mihailescu2m@gmail.com>
Change-Id: I3fb73f0f9a2f349fc667354a607c50ffefa7084e Signed-off-by: memeka <mihailescu2m@gmail.com>
…s for Exynos5422 Odroid boards Change-Id: I7f6dfebc2842f671f91cc9eb239f92b6cb2a03f9
This patch adds support irq mode in trip point. When that flag is set in DT, there is no need for polling in thermal framework. Crossing the trip point will rise an IRQ. The naming convention for tip point 'type' can be confussing and 'passive' (whic is passive cooling) might be interpretted wrongly. This mechanism prevents from missue and adds explicit setting for hardware which support interrupts for pre-configured temperature threshold. Change-Id: I2ee4c318bc74c07bfc3654ac9f3d6de4f2142088 Cc: Zhang Rui <rui.zhang@intel.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
Patch adds show functions for irq-mode feature. It allocates new attributes and extends the old list. Change-Id: I7966bfd783ac0abc78bb89c7ed5ee5fe61b2d1b9 Cc: Zhang Rui <rui.zhang@intel.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
…ode for Odroid XU3/4 1. Each A15 cores thermal sensor now correctly used and will trigger the fan or passive throttling as required. 2. Separate file used for trip points to allow unique labels per trip per cpu to be generated without having to duplicate the trips each time. Keeps code clear and allows for easy changes. 3. Trip points tweaked to optimise performance. A7's kept at full speed for longer since they contribute little to the thermal load. Efficiency is improved by not throttling them until required. A15's throttled earlier to manage performance better under heavy loads to extract maximum performance from the available cooling. 4. Cooling levels and temperature trip points tweaked by memeka Change-Id: I5353daa395ed5234dc955eab036956855e952ce0
…ode for Odroid HC1 Change-Id: I7e03be0fb60cd8948fa7bbde91789130b944a3b4 Signed-off-by: memeka <mihailescu2m@gmail.com>
Change directory name to be ready for new types of memories. Change-Id: If95f444fbca82d0735402e3427d14870ac9dc169 Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
Specifies the AC timing parameters of the LPDDR3 memory device. Change-Id: I05b121fb8eaa682afd88d383e38a9cfe9f6fa175 Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Change-Id: I42ab5749c048f38a6e64c8ce401311228de87c93 Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
…e description The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Change-Id: I50cc19ae01d34bd30890e0dc65bf741bc5bc0aad Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>
Add support for the SPICC controllers on the Amlogic G12A SoCs family. The G12A SPICC controllers inherit from the AXG enhanced registers but takes an external pclk for the baud rate generator and can achieve up to 166MHz SCLK. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I2e96db3e3fba657a3f136e7a4c70f369a11b77bc
This adds the controller and pinctrl nodes for the Amlogic G12A SPICC controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I771363f3be33ffaf1494b94fbe386bb57e69aa3c
This is the 5.4.26 stable release Change-Id: I17e5cc6e3d56815b49641ab1faa49d54db596c4a
This is the 5.4.27 stable release Change-Id: I7644a04e483462a9bd8abf69ffdc6dbeee1a3a0a
This is the 5.4.28 stable release Change-Id: I3a7e2ae7d99b146c1e0a7b9abe2df253d6f5ea6e
Change-Id: Idd9abac641030e5498171d88b3840349ce3b8442 Signed-off-by: Dongjin Kim <tobetter@gmail.com>
Change-Id: Ie5b40ea8885c324c81b4fa80a5bbe59b533b1b3a
Change-Id: Ibb6e79864c37a167d4861e02120d489a53c317e8
Change-Id: I129c3d059231a7941285deffc293ee72784adcce
Change-Id: I00e3748a6f8474a99d05200afc60b8d794f75c96
Change-Id: Ieced434cbde791edee600832f51bd5021b4604aa
Change-Id: Ia1c8c29d3f69c6ba5d630279c4cc98119b68ab71
This is the 5.4.29 stable release Change-Id: Ice27cc819d3c9d5c4b2756cbb48d200c56193d07
This is the 5.4.30 stable release Change-Id: I2f9290a3af771a562ac61b38c6c8aea6a240d7ca
This is the 5.4.31 stable release Change-Id: I4fd427325b102058f67c4085c89bc7b04c77e3d9
This is the 5.4.32 stable release Change-Id: Idd04e9be72497a88b91e69f6020102051959f20d
Change-Id: I67447bc3dc4222454c466fe7ab349357115b0a4f
Change-Id: I6ccc3714fce677b1eb104c10f657739320f3772f
Change-Id: Ib66a03da2fcf39fc459c20c9f98b1baca34dcf5b
Change-Id: Ifad96c7ab6935164402785ac9e6bf5d09fb42f82
This is the 5.4.33 stable release Change-Id: Ifeb3b6bb2110e6773a0ad6f234348eefa5713956
Change-Id: Ic9205e31eb8d3072fb9c4a20eac4c8e4d15664dc
…atible Set the appropriate gpio interrupt controller compatible for the sm1 SoC family. This newer version of the controller can now trig irq on both edge of the input signal Change-Id: Ie52e0f4f869c9bf8c198efa21e230a28ee31e04f Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Amlogic G12A and G12B SoCs integrate two thermal sensors with the same design. One is located close to the DDR controller and the other one is located close to the PLLs (between the CPU and GPU). The calibration data for each of the thermal sensors instance is stored in a different location within the AO region. Implement reading the temperature from each thermal sensor. The IP block has more functionality, which may be added to this driver in the future: - chip reset when the temperature exceeds a configurable threshold - up to four interrupts when the temperature has risen above a configurable threshold - up to four interrupts when the temperature has fallen below a configurable threshold Change-Id: I5f4cecbfd0796958d434bdeb051d5269b497c4d0 Tested-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20191004090114.30694-3-glaroque@baylibre.com
Fix up the following warning when compiled with make W=1: linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'A' not described in 'amlogic_thermal_soc_calib_data' linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'B' not described in 'amlogic_thermal_soc_calib_data' linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'm' not described in 'amlogic_thermal_soc_calib_data' linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'n' not described in 'amlogic_thermal_soc_calib_data' Change-Id: Iffb50455263d4151a6d65fa9df19edca8852ca65 Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/139c9191f1a18d528b5f94376facf40291d28244.1574242756.git.amit.kucheria@linaro.org
Add cpu and ddr temperature sensors for G12 Socs Change-Id: I4d30366f0d522d98d7ec6a46fdcd36f9c898b51c Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Tested-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Change-Id: I08a7bb6a12d3c4dcc023415bb66369b5d34899e9
Change-Id: I49b58c681dea5377df0ee7ab98163165d5521cb8
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Make it compatible with upstream > v5.7