Odroid-N2: arm64/dts: fix audio model name #394

Change-Id: I8e3e7707ac182f3956f7415a80876b9d4c8ac771

Add missing static qualifier to the chipid initcall function. Change-Id: I3d0b4b5d7710fe69e23a94637f640dff736f3661 Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…xynos5 All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable support for them directly in the base dtsi. None of the known firmware properly configures CNTFRQ arch timer register, so force clock frequency to 24MHz, which is the only configuration supported by the remaining clock drivers so far. Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset properly other arch timer registers, so add respective properties indicating that. Other Exynos5-based boards behaves correctly in this area, what finally allows to enable support for KVM-based virtualization. Change-Id: I87807b0bcd63d6d98f9765fd4cb9663ab5d221e9 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…2.0 PHY PHY calibration is needed only for USB2.0 (UTMI) PHY, so skip calling calibration code when phy_calibrate() is called for USB3.0 (PIPE3) PHY. Fixes: d8c80bb ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800") Change-Id: Ic3aaf6e70648e1a0a8177d3501f64c0ecfff2951 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Change-Id: Ia3c94b0ee99e761a774ac63398ca86477b703b8c Signed-off-by: Brian Kim <brian.kim@hardkernel.com> Signed-off-by: memeka <mihailescu2m@gmail.com> Signed-off-by: Dongjin Kim <tobetter@gmail.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…ild EDIDs - 480x800 60hz - 848x480 60hz - 1024x600 60hz (the old one is 1024x600p43hz) - 1152x864 75hz - 1280x768 60hz - 1400x1050 60hz - 1792x1344 60hz - 1920x800 60hz - 1920x1080 24Hz - 1920x1080 23.976Hz - 1920x1200 60hz - support for Vu5A - support for Vu7A+ new file: firmware/edid/480x800.bin new file: firmware/edid/640x480.bin new file: firmware/edid/720x480.bin new file: firmware/edid/720x576.bin new file: firmware/edid/800x480.bin new file: firmware/edid/800x600.bin new file: firmware/edid/848x480.bin new file: firmware/edid/1024x600.bin new file: firmware/edid/1024x768.bin new file: firmware/edid/1152x864_75hz.bin new file: firmware/edid/1280x1024.bin new file: firmware/edid/1280x720.bin new file: firmware/edid/1280x768.bin new file: firmware/edid/1280x800.bin new file: firmware/edid/1360x768.bin new file: firmware/edid/1366x768.bin new file: firmware/edid/1400x1050.bin new file: firmware/edid/1440x900.bin new file: firmware/edid/1600x1200.bin new file: firmware/edid/1600x900.bin new file: firmware/edid/1680x1050.bin new file: firmware/edid/1792x1344.bin new file: firmware/edid/1920x1080.bin new file: firmware/edid/1920x1080_23_976hz.bin new file: firmware/edid/1920x1080_24hz.bin new file: firmware/edid/1920x1080_50hz.bin new file: firmware/edid/1920x1200_30hz.bin new file: firmware/edid/1920x1200_60hz.bin new file: firmware/edid/1920x800.bin To support Vu5A, a pixel clock, 33.9MHz is needed. But, there is no exact hdmi phy table of exynos5422, so the cloest table will be used as a workaround. - Vu5A timing Detailed mode: Clock 33.900 MHz, 476 mm x 268 mm 800 844 932 1056 hborder 0 480 483 489 535 vborder 0 +hsync +vsync To support Vu7A+, a pixel clock, 49MHz is needed. But there is no exact hdmi phy table of exynos5422, so the closest table of 50.04MHz will be used as a workaround. - Vu7A+ timing Detailed mode (1) : Clock 49 MHz, 255 mm x 255 mm 1024 1029 1042 1312 hborder 0 600 602 605 622 vborder 0 -hsync +vsync - 1024x600 60hz timing Detailed mode: Clock 50.400 MHz, 355 mm x 208 mm 1024 1048 1184 1344 hborder 0 600 601 604 625 vborder 0 -hsync +vsync Change-Id: I1278be0ef8812d709429f02f1738c73033e2d5a0 Signed-off-by: memeka <mihailescu2m@gmail.com>

On Exynos there is a solid color plane that is logically below all the other display planes. This causes display artifacts due to alpha. The patch disables blending the base plane with the solid color plane (no alpha). Change-Id: Ibb2ada1d7a7be156d2f05ed477ee5972d63edd98 Reviewed-by: memeka <mihailescu2m@gmail.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Change-Id: Ia83449849d4636baf57ed64d7183c2a9cec7fe22 Signed-off-by: memeka <mihailescu2m@gmail.com>

Change-Id: Ida63e217cd989d661b7620d390515c0ffcb830ac Signed-off-by: memeka <mihailescu2m@gmail.com>

…acks This patch moves vb2_dc_get_base_sgt() function above mmap buffers callbacks, particularly vb2_dc_alloc() and vb2_dc_mmap() from where it will be called for cacheable MMAP support introduced in the next patch. Change-Id: Ia504fbc1f0b3741986e8fff1ad329215b6e2db2e Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

DMA allocations for MMAP type are uncached by default. But for some cases, CPU has to access the buffers. ie: memcpy for format converter. Supporting cacheable MMAP improves huge performance. This patch enables cacheable memory for DMA coherent allocator in mmap buffer allocation if non-consistent DMA attribute is set and kernel mapping is present. Even if userspace doesn't mmap the buffer, sync still should be happening if kernel mapping is present. If not done in allocation, it is enabled when memory is mapped from userspace (if non-consistent DMA attribute is set). Change-Id: I1e8e65086a2e4511563e8e7c3748d3b5403f18c3 Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Tested-by: Heng-ruey Hsu <henryhsu@chromium.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Thierry Escande <thierry.escande@collabora.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Change-Id: I6b574d2a73ed0cda41e19f1e4982828f8f591177 Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…ormance Change-Id: I2054a87278e545515be927ddcc52f52991224a6e Signed-off-by: memeka <mihailescu2m@gmail.com>

…tput Change-Id: Ic3a2f6eb94d60604df50976eca4e210898f40b32 Signed-off-by: memeka <mihailescu2m@gmail.com>

If streaming is active when the MFC device is closed, it will generate an IOMMU page-fault. Change-Id: Ie5c664ecddaebedf282eae1d56e82821b5883ffd Signed-off-by: memeka <mihailescu2m@gmail.com>

Add new table rate for VPLL for Exynos 542x SoC required to support Mali GPU clock frequencies. Change-Id: I71303661fe2f66840386028ef2a53f2242073eef

…cks on G3D path Add CLK_SET_RATE_PARENT flag to all clocks on the path from VPLL to G3D, so the G3D MALI driver can simply adjust the rate of its clock by doing a single clk_set_rate() call, without the need to know the whole clock topology in Exynos542x SoCs. Change-Id: I0506b4cf9c5318ee8d16a5122a21e0bf8ad20e62 Suggested-by: Marian Mihailescu <mihailescu2m@gmail.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

All top clocks on G3D path has to be enabled all the time to allow proper G3D power domain operation. This is achieved by adding CRITICAL flag to "mout_sw_aclk_g3d" clock, what keeps this clock and all its parents enabled. This fixes following imprecise abort issue observed on Odroid XU3/XU4 after enabling Panfrost driver by commit 1a5a85c "ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4"): panfrost 11800000.gpu: clock rate = 400000000 panfrost 11800000.gpu: failed to get regulator: -517 panfrost 11800000.gpu: regulator init failed -517 Power domain G3D disable failed ... panfrost 11800000.gpu: clock rate = 400000000 8<--- cut here --- Unhandled fault: imprecise external abort (0x1406) at 0x00000000 pgd = (ptrval) [00000000] *pgd=00000000 Internal error: : 1406 [hardkernel#1] PREEMPT SMP ARM Modules linked in: CPU: 7 PID: 53 Comm: kworker/7:1 Not tainted 5.4.0-rc8-next-20191119-00032-g56f1001191a6 #6923 Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) Workqueue: events deferred_probe_work_func PC is at panfrost_gpu_soft_reset+0x94/0x110 LR is at ___might_sleep+0x128/0x2dc ... [<c05c231c>] (panfrost_gpu_soft_reset) from [<c05c2704>] (panfrost_gpu_init+0x10/0x67c) [<c05c2704>] (panfrost_gpu_init) from [<c05c15d0>] (panfrost_device_init+0x158/0x2cc) [<c05c15d0>] (panfrost_device_init) from [<c05c0cb0>] (panfrost_probe+0x80/0x178) [<c05c0cb0>] (panfrost_probe) from [<c05cfaa0>] (platform_drv_probe+0x48/0x9c) [<c05cfaa0>] (platform_drv_probe) from [<c05cd20c>] (really_probe+0x1c4/0x474) [<c05cd20c>] (really_probe) from [<c05cd694>] (driver_probe_device+0x78/0x1bc) [<c05cd694>] (driver_probe_device) from [<c05cb374>] (bus_for_each_drv+0x74/0xb8) [<c05cb374>] (bus_for_each_drv) from [<c05ccfa8>] (__device_attach+0xd4/0x16c) [<c05ccfa8>] (__device_attach) from [<c05cc110>] (bus_probe_device+0x88/0x90) [<c05cc110>] (bus_probe_device) from [<c05cc634>] (deferred_probe_work_func+0x4c/0xd0) [<c05cc634>] (deferred_probe_work_func) from [<c0149df0>] (process_one_work+0x300/0x864) [<c0149df0>] (process_one_work) from [<c014a3ac>] (worker_thread+0x58/0x5a0) [<c014a3ac>] (worker_thread) from [<c0151174>] (kthread+0x12c/0x160) [<c0151174>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) Exception stack(0xee03dfb0 to 0xee03dff8) ... Code: e594300c e5933020 e3130c01 1a00000f (ebefff50). ---[ end trace badde2b74a65a540 ]--- In the above case, the Panfrost driver disables G3D clocks after failure of getting the needed regulator and return with -EPROVE_DEFER code. This causes G3D power domain disable failure and then, during second probe an imprecise abort is triggered due to undefined power domain state. Fixes: 45f10da ("clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path") Fixes: c9f7567 ("clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Change-Id: Ic999b9c06b43a3fa148ab254ccef518cecc99460 Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>

… Odroid XU3/4 Add device tree node for Mali GPU for Exynos 542x SoC. GPU is disabled by default, and is enabled for each board after the regulator is defined. Tested on Odroid-XU4. Change-Id: I902932d29c7093b666fa3a8a8e1d0fda8fb11d5c Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>

…422 TMU Change-Id: I6014d6d3fdecb6f58c6160f79ac969c6816f365d Signed-off-by: memeka <mihailescu2m@gmail.com>

Change-Id: I3fb73f0f9a2f349fc667354a607c50ffefa7084e Signed-off-by: memeka <mihailescu2m@gmail.com>

…s for Exynos5422 Odroid boards Change-Id: I7f6dfebc2842f671f91cc9eb239f92b6cb2a03f9

This patch adds support irq mode in trip point. When that flag is set in DT, there is no need for polling in thermal framework. Crossing the trip point will rise an IRQ. The naming convention for tip point 'type' can be confussing and 'passive' (whic is passive cooling) might be interpretted wrongly. This mechanism prevents from missue and adds explicit setting for hardware which support interrupts for pre-configured temperature threshold. Change-Id: I2ee4c318bc74c07bfc3654ac9f3d6de4f2142088 Cc: Zhang Rui <rui.zhang@intel.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Patch adds show functions for irq-mode feature. It allocates new attributes and extends the old list. Change-Id: I7966bfd783ac0abc78bb89c7ed5ee5fe61b2d1b9 Cc: Zhang Rui <rui.zhang@intel.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…ode for Odroid XU3/4 1. Each A15 cores thermal sensor now correctly used and will trigger the fan or passive throttling as required. 2. Separate file used for trip points to allow unique labels per trip per cpu to be generated without having to duplicate the trips each time. Keeps code clear and allows for easy changes. 3. Trip points tweaked to optimise performance. A7's kept at full speed for longer since they contribute little to the thermal load. Efficiency is improved by not throttling them until required. A15's throttled earlier to manage performance better under heavy loads to extract maximum performance from the available cooling. 4. Cooling levels and temperature trip points tweaked by memeka Change-Id: I5353daa395ed5234dc955eab036956855e952ce0

…ode for Odroid HC1 Change-Id: I7e03be0fb60cd8948fa7bbde91789130b944a3b4 Signed-off-by: memeka <mihailescu2m@gmail.com>

Change directory name to be ready for new types of memories. Change-Id: If95f444fbca82d0735402e3427d14870ac9dc169 Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Specifies the AC timing parameters of the LPDDR3 memory device. Change-Id: I05b121fb8eaa682afd88d383e38a9cfe9f6fa175 Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

The patch adds AC timings information needed to support LPDDR3 and memory controllers. The structure is used in of_memory and currently in Exynos 5422 DMC. Add parsing data needed for LPDDR3 support. It is currently used in Exynos5422 Dynamic Memory Controller. Change-Id: I42ab5749c048f38a6e64c8ce401311228de87c93 Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…e description The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. Change-Id: I50cc19ae01d34bd30890e0dc65bf741bc5bc0aad Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. There is also an algorithm to calculate timigns based on memory description provided in DT. The patch also contains needed MAINTAINERS file update. Change-Id: I6b81edf71772f9dd8ed3fde27b64cba9bbb29042 Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

In order to get the clock by phandle and use it with regmap it needs to be compatible with syscon. The DMC driver uses two registers from clock register set and needs the regmap of them. Change-Id: I5f844e15214928b1b2240c4df9802a1924f207d3 Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. There is a definition of the memory chip, which is then used during calculation of timings for each OPP. The algorithm in the driver needs these two sets to bound the timings. Change-Id: Icd26d77033c2e1e4e71f28e64f5b126d865bdbbc Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Enable driver for Exynos5422 Dynamic Memory Controller supporting dynamic frequency and voltage scaling in Exynos5422 SoCs. Change-Id: Ib31c2789a5a87823a5441d922f3aec5c8696e187 Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…cated memory and missing static Fix issues captured by static checkers: used kfree() and missing 'static' in the private function. Fixes Smatch warning: drivers/memory/samsung/exynos5422-dmc.c:272 exynos5_init_freq_table() warn: passing devm_ allocated variable to kfree. 'dmc->opp' Fixes Sparse warning: drivers/memory/samsung/exynos5422-dmc.c:736:1: warning: symbol 'exynos5_dmc_align_init_freq' was not declared. Change-Id: I98f7b908abc26f17187c771f668b7bf64658be38 Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Add compatible for Samsung k3qf2f20db LPDDR3 memory bindings. Suggested to based on at25.txt compatible section. Introduce minor fixes in the old documentation. Change-Id: I48f8025c745f95cbd4b29cf2ad04d77cac685a1f Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…rupts description Add description for optional interrupt lines. It provides a new operation mode, which uses internal performance counters interrupt when overflow. This is more reliable than using default polling mode implemented in devfreq. Change-Id: I3be940bc4d49620cd63287c8be8ccf6f73ba3d24 Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…os5422 Add interrupt to Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards. It will be used instead of devfreq polling mode governor. The interrupt is connected to performance counters private for DMC, which might track utilisation of the memory channels. Change-Id: I2b4680ff82a7ff2fc038196c197c85f33b258359 Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

… Exynos5422 There is a need to access registers at address offset near 0x10000. These registers are private DMC performance counters, which might be used as interrupt trigger when overflow. Potential usage is to skip polling in devfreq framework and switch to interrupt managed bandwidth control. Change-Id: Iba1fd2397507b313f190e9232f0fab791fc28a3a Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…t from performance counters Introduce a new interrupt driven mechanism for managing speed of the memory controller. The interrupts are generated due to performance counters overflow. The performance counters might track memory reads, writes, transfers, page misses, etc. In the basic algorithm tracking read transfers and calculating memory pressure should be enough to skip polling mode in devfreq. Change-Id: Idb5deaa423d75a9a0961b64f9f9514d6ce7c95c1 Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…example syntax and memory region After adding the interrupt properties to Exynos5422 DMC bindings example, the mapped memory region must be big enough to access performance counters registers. Fix also syntax errors (semicolons) and adjust indentation. Change-Id: Ibbf0579f8aa76c56d9cee48809ed341e3561d383 Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

The CHIP ID block in addition to exact chip revision information contains data and control registers for ASV (Adaptive Supply Voltage) and ABB (Adaptive Body Bias). Add "syscon" compatible so the CHIPID block can be shared by respective drivers. Change-Id: Id7469143417eac92f1f7d010004b67ae6ed35e8d Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

The Exynos5422 SoC used on Odroid XU3 Lite boards belongs to a special ASV bin but this information cannot be read from the CHIPID block registers. Add samsung,asv-bin property for XU3 Lite to ensure the ASV bin is properly determined. Change-Id: I6e977b9cf0829be7ffff5aa84d7ee6b3e65b49cd Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

… to json-schema Convert Samsung Exynos Chipid bindings to DT schema format using json-schema. Change-Id: Ia6906a3f50d6f0a791fdd3e6e583e92a08716e4b Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: memeka <mihailescu2m@gmail.com>

On some SoCs the Adaptive Voltage Scaling (AVS) technique is employed to optimize the operating voltage of a device. At a given frequency, the hardware monitors dynamic factors and either makes a suggestion for how much to adjust a voltage for the current frequency, or it automatically adjusts the voltage without software intervention. Add an API to the OPP library for the former case, so that AVS type devices can update the voltages for an OPP when the hardware determines the voltage should change. The assumption is that drivers like CPUfreq or devfreq will register for the OPP notifiers and adjust the voltage according to suggestions that AVS makes. This patch is derived from [1] submitted by Stephen. [1] https://lore.kernel.org/patchwork/patch/599279/ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Roger Lu <roger.lu@mediatek.com> [s.nawrocki@samsung.com: added handling of OPP min/max voltage] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com> Change-Id: I172ca9d88d40e97216eeac76ba3e74f12f984765

This patch adds documentation of new optional "samsung,asv-bin" property in the chipid device node and documents requirement of "syscon" compatible string. These additions are needed to support Exynos ASV (Adaptive Supply Voltage) feature. Change-Id: Ib51dbc3ad36705abc3df17a6b80a614a0b28c215 Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: memeka <mihailescu2m@gmail.com>

The Adaptive Supply Voltage (ASV) driver adjusts CPU cluster operating points depending on exact revision of an SoC retrieved from the CHIPID block or the OTP memory. This allows for some power saving as for some CPU clock frequencies we can lower CPU cluster's supply voltage comparing to safe values common to all the SoC revisions. This patch adds support for Exynos5422/5800 SoC, it is partially based on code from https://github.com/hardkernel/linux repository, branch odroidxu4-4.14.y, files: arch/arm/mach-exynos/exynos5422-asv.[ch]. Tested on Odroid XU3, XU4, XU3 Lite. Change-Id: I1cfc9324ba11a77ebccbca1176caa28abb2527de Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Enable exynos-asv driver for Exynos 32-bit SoCs. Change-Id: Ifa8152915fda8f4c1c36dc11c96c8804ea6860dd Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

…ors on Exynos5422/5800 SoCs Commit 4294a77 ("PM / devfreq: exynos-bus: Convert to use dev_pm_opp_set_rate()") introduced errors: exynos-bus: new bus device registered: soc:bus_wcore ( 84000 KHz ~ 400000 KHz) exynos-bus: new bus device registered: soc:bus_noc ( 67000 KHz ~ 100000 KHz) exynos-bus: new bus device registered: soc:bus_fsys_apb (100000 KHz ~ 200000 KHz) ... exynos-bus soc:bus_wcore: dev_pm_opp_set_rate: failed to find current OPP for freq 532000000 (-34) exynos-bus soc:bus_noc: dev_pm_opp_set_rate: failed to find current OPP for freq 111000000 (-34) exynos-bus soc:bus_fsys_apb: dev_pm_opp_set_rate: failed to find current OPP for freq 222000000 (-34) They are caused by incorrect PLL assigned to clock source, which results in clock rate outside of OPP range. Add workaround for this in exynos_bus_parse_of() by adjusting clock rate to those present in OPP. Fixes: 4294a77 ("PM / devfreq: exynos-bus: Convert to use dev_pm_opp_set_rate()") Change-Id: Ic07e2d68e0da2efa07cb81cc9b4f76d8ad15bd76 Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com> Signed-off-by: memeka <mihailescu2m@gmail.com>

Added .shutdown function to s2mps11 to help poweroff the board successfully. The device driver clears the register to turn off the PMIC. s2mps11-pmic: S2MPS11_REG_CTRL1 reg value 16:00000000000000000000000000010000 Console log. * Unmounting temporary filesystems... [ OK ] * Deactivating swap... [ OK ] * Unmounting local filesystems... [ OK ] * Will now halt [ 209.020280] reboot: Power down [ 209.122039] Power down failed, please power off system manually. Change-Id: If6ea0dec154b00ceeaaddbac393c67dc35c26279 Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: memeka <mihailescu2m@gmail.com> Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>

…function Ethernet device cannot be detected on warm boot sometimes. This patch is to add the power reset routines for ethernet device using PMIC. Then ethernet device can be reset hardware-wise. Change-Id: Iffbe2966da7e4679f63b91ab79241167391792df Signed-off-by: Brian Kim <brian.kim@hardkernel.com> Signed-off-by: Marian Mihailescu <mihailescu2m@gmail.com>

Change-Id: Ifa5b2f4730d96071f11931f4719c86c624f60194

Change-Id: If702a43a1cf8cdc1b322f925c8f8061ed106f1d2

Original config contents from @rooted. Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: Ic49dc77fbbeff490f4995a87d633d83374782447

Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: Ibd89677ca9dcc165b305488b9c1e106f4e53eba6

Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I0b1d16b0f445838509eeb0cc8093239fa1805605

…PIO access Signed-off-by: memeka <mihailescu2m@gmail.com> Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: Ia6b9596501223037ee3be3587d720f74a2494380

wiringPi library refers to this information in '/proc/cpuinfo' file. Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I4a3368499cecf862eddb1430c6b436283f62d2c7

Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I506c7e34ba3be12b2934340667a7c6c42744c56c

Change-Id: Ice75e06366f107f761504512a84fb92affffb124 Signed-off-by: Dongjin Kim <tobetter@gmail.com>

Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I7d141a655c23bf364753be9831b4428ee3aa6711

…tion Because the other devices we provided have vendor name in /proc/cpuinfo. Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I81a553ea8f662016b702cbb5e543ba7a769e8d0f

…ed when every time it opens Change-Id: If35e49c6d96b960f0ff1a997b2126c2c6378fdad Signed-off-by: Yang Deokgyu <secugyu@gmail.com>

…nch TFT LCD No longer use flexfb, fbtft_device that is deprecated since kernel 5.4. Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: Iae252c64b91b2eabe97eb3aace12d7c4b98801c5

…nch TFT LCD No longer use flexfb, fbtft_device that is deprecated since kernel 5.4. Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: Iebd014360f90eab5210722102d54c6169be5e28e

Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I8441bb567a119ca51281a4aefec7f72bf79f6f04

… OGST It doesn't include its touchscreen yet. Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I110e897746dea17fc32e9fdc442c492d70888dfa

Copy *.dtbo files at arch/arm/boot/dts/overlays to boot partition, e.g, /media/boot/overlays/. Then use "fdtoverlay" tool to integrate DTB and DTBOs. Or, you also can use "fdt apply" u-boot command to prepare device tree blob at booting time. Signed-off-by: Yang Deokgyu <secugyu@gmail.com> Change-Id: I40e6a915e2149952fb548f64e7fae335ba12db18

… SS instances in park mode This patch updates the documentation with the information related to the quirks that needs to be added for disabling all SuperSpeed XHCi instances in park mode. Change-Id: I187aa6a4a3964cbb356d458cce8d5a5fa4eeb70f CC: Dongjin Kim <tobetter@gmail.com> Cc: Jianxin Pan <jianxin.pan@amlogic.com> Reported-by: Tim <elatllat@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Rob Herring <robh@kernel.org>

…in park mode In certain circumstances, the XHCI SuperSpeed instance in park mode can fail to recover, thus on Amlogic G12A/G12B/SM1 SoCs when there is high load on the single XHCI SuperSpeed instance, the controller can crash like: xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. xhci-hcd xhci-hcd.0.auto: Host halt failed, -110 xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. hub 2-1.1:1.0: hub_ext_port_status failed (err = -22) xhci-hcd xhci-hcd.0.auto: HC died; cleaning up usb 2-1.1-port1: cannot reset (err = -22) Setting the PARKMODE_DISABLE_SS bit in the DWC3_USB3_GUCTL1 mitigates the issue. The bit is described as : "When this bit is set to '1' all SS bus instances in park mode are disabled" Change-Id: I57f23e886f688a00a02ff9f1065dcb1e30d3e0f9 CC: Dongjin Kim <tobetter@gmail.com> Cc: Jianxin Pan <jianxin.pan@amlogic.com> Reported-by: Tim <elatllat@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

…WC3 controller When high load on the DWC3 SuperSpee port, the controller crashed as: [ 221.141621] xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. [ 221.157631] xhci-hcd xhci-hcd.0.auto: Host halt failed, -110 [ 221.157635] xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead [ 221.159901] xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command. [ 221.159961] hub 2-1.1:1.0: hub_ext_port_status failed (err = -22) [ 221.160076] xhci-hcd xhci-hcd.0.auto: HC died; cleaning up [ 221.165946] usb 2-1.1-port1: cannot reset (err = -22) Setting the parkmode_disable_ss_quirk quirk fixes the issue. Change-Id: Ibdee33392e47b6ce12d08ad7ae236f670f658a2d CC: Dongjin Kim <tobetter@gmail.com> Cc: Jianxin Pan <jianxin.pan@amlogic.com> Reported-by: Tim <elatllat@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Change-Id: I361804b497d71fd67a4c6816463d5cac607e0a53 Signed-off-by: Dongjin Kim <tobetter@gmail.com>

Add the property describing the depth of the audio fifo on the axg, g12a and sm1 SoC family Change-Id: I2711ce8f51fec2a4773e84c3deb61ae585bb5932 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I046d3dcb7d5aab04c34af842c82bc2b078cf07b4 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: Ic77cbfc74716e2ecf1d84190ba76b01b647ff958 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I870277d45e299abf291b8cc9883a8b9f7cbf965a Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: If5a06aa72e0e80466425322c21ce4e172b5e123b Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I248cec1fed97794fe9874422d2c023a53ff667c6 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I7ea9dd632ed751fcb80f0c2b26cabacda3352ea3 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: Ida7959b0b7e06190108222cba4ad1440cbf6c4fd Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: Ic7d09523a3e57a8fd55651745a116621bcd6166f Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

The AIU is audio playback subsystem of the legacy Amlogic SoC, such as the gxbb, gxl and gxm family. Blabla Change-Id: Ieff0fb6fe915de7bc2c4768b2c193f550d18b05e Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I9cc824782030a4e991222fcfb9e34939572c5df3 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I5c10733e224b18f5ac647f15aa2f7c56b25112fa Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I0b9c9daa55913de09e8304b362e1461c9034aea7 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: Ia187b1527ec22bcb6dce7011f3894ba2f19e6ef1 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I9c855880eb02f4d08cc0d615b3a1773fd3f66eab Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I664b15a1ed5fce7c626bca74f6c10ccbdd68ef06 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

FIXME: Missing gxbb ATM Change-Id: I70690bc4a3d17f67e30d8e6efca7d26fff046eaa Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

FIXME Change-Id: I5cbae727b2f9ca88625b9534333bc075267a639f Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: Ifc4aadc0ae850537a8e7e35b20e5455ba46bcf98 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

Change-Id: I2add8a7238f94a4eddab312c6ccb75559823c981 Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

The dai codec needs to ensure that on one dai is used at any time. This is currently protected by bit atomic operation. With this change, it done with a mutex instead. Change-Id: I939c1f1eb9eec919f6616ad2286dd7937b978e47 Suggested-by: Mark Brown <broonie@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

…k hdmi output. Change-Id: I4d43b802815779687ade974f049f2b0517a411d1 Signed-off-by: ckkim <changkon12@gmail.com>

Change-Id: Iec7786278aae48bd9d8a4efbf56073b88ed9f1d8 Signed-off-by: ckkim <changkon12@gmail.com>

Change-Id: I17dc037f9225c8aa07129f28d3be9bd7c9dc1177 Signed-off-by: ckkim <changkon12@gmail.com>

Change-Id: Ifc5e79e61052cc95895ff0325b4b18128e187a31 Signed-off-by: ckkim <changkon12@gmail.com>

…e powered off" FIXME: this patch crashes when Mali is activated This reverts commit f44b074. Change-Id: I2f3e8e68b3172c2c1d035032b47fb256c5757be8

This is the 5.4.23 stable release Change-Id: I3879d830f0f5f1fc746d80ec0ab99cb5fcc10b08

This is the 5.4.24 stable release Change-Id: I411c47f6ac9624aaa81d62dc31b8cf45b73a06ce

Change-Id: Idcec2c95970c75aca00c30726b4e007ad1651a13 Signed-off-by: Dongjin Kim <tobetter@gmail.com>

This is the 5.4.25 stable release Change-Id: I4154f610e40ce5be6010f67dfbafdf9a1ece36aa

Signed-off-by: ckkim <changkon12@gmail.com> Change-Id: I52bbf26aaf807e96bff7665bb65a1ee5594f6449

This patch removes the write-protect pin from SD card since it's not being supported by a hardware and used at all. Signed-off-by: ckkim <changkon12@gmail.com> Change-Id: I72af94f7fd0a01e65f7ca3e15ccd66e797395df4

Change-Id: I6092834427950a50746535458e99bf7089212044

Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Change-Id: Ib8ca9620bf18bbc10a6d0bca8948c09cecfdb824

…ocks This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC controller to provide a more complete range of frequencies instead of the SPICC internal divider over Xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I83faaa233aa68728f1ac99decb2cbc57713f984f

Remove unused variables from spicc data struct. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I40e3cb7e5106717391839296d6a18057ec968ce4

The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS signal lines through the idle state (between two transmission operation), which avoid the signals floating in unexpected state. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I8b54798e3f1b726e4e373a8d5a150ce6f8806399

The SPICC controller in Meson-AXG SoC is capable of using a linear clock divider to reach a much fine tuned range of clocks, while the old controller only use a power of two clock divider, result at a more coarse clock range. Also convert the clock registration into Common Clock Framework. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: Ic532909d504163b151bff8b91fde51bc9fbb960c

The SPICC controller in Meson-AXG is capable of running at 80M clock. The ASIC IP is improved and the clock is actually running higher than previous old SoCs. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: Ib9908321efb931a142112e4d374f139c12f468ed

The G12A SPICC controller variant takes the source clock from a specific clock instead of the bus clock. The minimal clock calculus won't work with the G12A support, thus add the minimal supported clock for each variant and pass this to the SPI core. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I20b4245fa0984f22412d28815456e78e93697158

Now the controller can support frequencies higher than 30MHz, we need the setup the I/O line delays in regard of the SPI clock frequency. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I10a98c33e0bdd10e51101bd6d226d790b2061232

The G12A SPICC controller variant has a different FIFO size and doesn't handle the RX Half interrupt the same way as GXL & AXG variants. Thus simplify the burst management and take in account a variable FIFO size. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: Iff57ebdac5cc0a2a5a4863d82619ab9ef7a77fd3

…A compatible The Amlogic G12A SPICC controllers uses a secondary clock used to feed the baud rate generator and the delay control logic. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I0183ea1d2daab02167477ed6799eca3587759d80

Add support for the SPICC controllers on the Amlogic G12A SoCs family. The G12A SPICC controllers inherit from the AXG enhanced registers but takes an external pclk for the baud rate generator and can achieve up to 166MHz SCLK. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I2e96db3e3fba657a3f136e7a4c70f369a11b77bc

This adds the controller and pinctrl nodes for the Amlogic G12A SPICC controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Change-Id: I771363f3be33ffaf1494b94fbe386bb57e69aa3c

This is the 5.4.26 stable release Change-Id: I17e5cc6e3d56815b49641ab1faa49d54db596c4a

This is the 5.4.27 stable release Change-Id: I7644a04e483462a9bd8abf69ffdc6dbeee1a3a0a

This is the 5.4.28 stable release Change-Id: I3a7e2ae7d99b146c1e0a7b9abe2df253d6f5ea6e

Change-Id: Idd9abac641030e5498171d88b3840349ce3b8442 Signed-off-by: Dongjin Kim <tobetter@gmail.com>

Change-Id: Ie5b40ea8885c324c81b4fa80a5bbe59b533b1b3a

Change-Id: Ibb6e79864c37a167d4861e02120d489a53c317e8

Change-Id: I129c3d059231a7941285deffc293ee72784adcce

Change-Id: I00e3748a6f8474a99d05200afc60b8d794f75c96

Change-Id: Ieced434cbde791edee600832f51bd5021b4604aa

Change-Id: Ia1c8c29d3f69c6ba5d630279c4cc98119b68ab71

This is the 5.4.29 stable release Change-Id: Ice27cc819d3c9d5c4b2756cbb48d200c56193d07

This is the 5.4.30 stable release Change-Id: I2f9290a3af771a562ac61b38c6c8aea6a240d7ca

This is the 5.4.31 stable release Change-Id: I4fd427325b102058f67c4085c89bc7b04c77e3d9

This is the 5.4.32 stable release Change-Id: Idd04e9be72497a88b91e69f6020102051959f20d

Change-Id: I67447bc3dc4222454c466fe7ab349357115b0a4f

Change-Id: I6ccc3714fce677b1eb104c10f657739320f3772f

Change-Id: Ib66a03da2fcf39fc459c20c9f98b1baca34dcf5b

Change-Id: Ifad96c7ab6935164402785ac9e6bf5d09fb42f82

This is the 5.4.33 stable release Change-Id: Ifeb3b6bb2110e6773a0ad6f234348eefa5713956

Change-Id: Ic9205e31eb8d3072fb9c4a20eac4c8e4d15664dc

…atible Set the appropriate gpio interrupt controller compatible for the sm1 SoC family. This newer version of the controller can now trig irq on both edge of the input signal Change-Id: Ie52e0f4f869c9bf8c198efa21e230a28ee31e04f Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Amlogic G12A and G12B SoCs integrate two thermal sensors with the same design. One is located close to the DDR controller and the other one is located close to the PLLs (between the CPU and GPU). The calibration data for each of the thermal sensors instance is stored in a different location within the AO region. Implement reading the temperature from each thermal sensor. The IP block has more functionality, which may be added to this driver in the future: - chip reset when the temperature exceeds a configurable threshold - up to four interrupts when the temperature has risen above a configurable threshold - up to four interrupts when the temperature has fallen below a configurable threshold Change-Id: I5f4cecbfd0796958d434bdeb051d5269b497c4d0 Tested-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20191004090114.30694-3-glaroque@baylibre.com

Fix up the following warning when compiled with make W=1: linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'A' not described in 'amlogic_thermal_soc_calib_data' linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'B' not described in 'amlogic_thermal_soc_calib_data' linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'm' not described in 'amlogic_thermal_soc_calib_data' linux.git/drivers/thermal/amlogic_thermal.c:78: warning: Function parameter or member 'n' not described in 'amlogic_thermal_soc_calib_data' Change-Id: Iffb50455263d4151a6d65fa9df19edca8852ca65 Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/139c9191f1a18d528b5f94376facf40291d28244.1574242756.git.amit.kucheria@linaro.org

Add cpu and ddr temperature sensors for G12 Socs Change-Id: I4d30366f0d522d98d7ec6a46fdcd36f9c898b51c Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Tested-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Change-Id: I08a7bb6a12d3c4dcc023415bb66369b5d34899e9

Change-Id: I49b58c681dea5377df0ee7ab98163165d5521cb8

Commits on Apr 27, 2020

Odroid-N2: arm64/dts: fix audio model name

pvizeli committed Apr 27, 2020

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Odroid-N2: arm64/dts: fix audio model name #394

Odroid-N2: arm64/dts: fix audio model name #394

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Odroid-N2: arm64/dts: fix audio model name #394

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Odroid-N2: arm64/dts: fix audio model name #394

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