armstub8: Initialize CPTR_EL3 with zeros (#123)

In both Cortex A53 and A72, every bit of CPTR_EL3 is RES0 except bit 10 and bit 31. We need bit 10 to be 0, also bit 31 is 0 previously, so zero the entire register in initialization.
raspberrypi · Jul 5, 2021 · 2e59fc6 · 2e59fc6
1 parent fc0e73c
commit 2e59fc6
Showing 1 changed file with 2 additions and 3 deletions.
diff --git a/armstubs/armstub8.S b/armstubs/armstub8.S
@@ -115,9 +115,8 @@ _start:
 	msr CNTVOFF_EL2, xzr
 
 	/* Enable FP/SIMD */
-	/* All set bits below are res1; bit 10 (TFP) is set to 0 */
-	mov x0, #0x33ff
-	msr CPTR_EL3, x0
+	/* Bit 10 (TFP) is set to 0 */
+	msr CPTR_EL3, xzr
 
 	/* Set up SCR */
 	mov x0, #SCR_VAL