acceleration_examples

acceleration_examples is a meta-package that contain various ROS packages examples demonstrating the use of hardware acceleration. Each one of these examples aims to support all hardware acceleration technology solutions complying with REP-2008 (see pending PR). By doing so, acceleration_examples aims to a) illustrate ROS package maintainers and ROS users how to build their own acceleration kernels and b) guarantee interoperability across technologies complying with REP-2008.

In turn, a CI system will be set to build the meta-package against all suported hardware.

Package	Kernel	Description	Acceleration factor	Technology	CPU baseline	Accelerated
publisher_xilinx		This package contains a minimalistic publisher using a member function for evaluation purposes which subclasses rclcpp::Node and sets up an rclcpp::timer to periodically call functions which publish messages.
simple_adder	adder1 adder2	A trivial adder example. No interactions with the ROS 2 computational graph. Meant to demonstrate how HLS is integrated into build ROS 2 flows.	N/A	KV260	N/A
vadd_publisher		A a trivial vector-add ROS 2 publisher. Adds two inputs to a vector in a loop and tries publishing it on the go at 10 Hz.		KV260	10 Hz1
doublevadd_publisher		A trivial double vector-add ROS 2 publisher. Adds two inputs to a vector in a loop and publishes on the go at 10 Hz. Running in hardware shows that it's not able to meet the rate target and stays at around 2 Hz. The objective of this package is to generate a computationally expensive baseline when executed in a general purpose embedded CPU. See accelerated_doublevadd_publisher package for an optimized and accelerated version of the same package which offloads the vector operations into an FPGA. See faster_doublevadd_publisher for an even more optimized version.		KV260	2 Hz1
offloaded_doublevadd_publisher	vadd	An offloaded version of the trivial doublevadd_publisher ROS 2 publisher which adds two inputs to a vector in a loop and publishes them at 10 Hz. Vector add operations are directly offloaded into to the FPGA (i.e. a kernel is created out of C++, without any modifications). The offloading operation shows how while guaranteeing determinsm in the vadd operation context, simple offloading to the FPGA lowers the publishing rate from 2 Hz (in the CPU) to 1.5 Hz due the slower clock that the FPGA uses	0.75x	KV260	2 Hz1	1.5 Hz1
accelerated_vadd_publisher	vadd	An dataflow optimized offloaded version of the trivial doublevadd_publisher ROS 2 publisher which adds two inputs to a vector in a loop and publishes them at 10 Hz. Vector add operations are offloaded into to the FPGA and some minor dataflow optimizations are applied using HLS. The offloading operation into the FPGA allows the publisher to go from 2 Hz to 6 Hz but, still misses its target (10 Hz)	3x	KV260	2 Hz1	6 Hz1
faster_doublevadd_publisher	vadd	An accelerated version of the trivial doublevadd_publisher ROS 2 publisher which adds two inputs to a vector in a loop and publishes them at 10 Hz. Vector add operations are accelerated by exploiting parallelism with the FPGA. Also, similarly to accelerated_doublevadd_publisher, some basic dataflow optimizations are performed. The code parallelism and dataflow optimizations of the dataflow allows the publisher to go from 2 Hz to 10 Hz, meeting its target	5x	KV260	2 Hz1	10 Hz1

• 1: measured with ros2 topic hz <topic-name>
• 2: very low rate.

Quality Declaration

No quality is claimed according to REP-2004. This meta-package is designed as a learning and reference resource and it should not be used in production environments.