[Mellanox][202012] Support Mellanox-SN4600C-C64 as T1 switch in dual-ToR scenario #11032
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Signed-off-by: Stephen Sun <stephens@nvidia.com>
Signed-off-by: Stephen Sun <stephens@nvidia.com>
Signed-off-by: Stephen Sun <stephens@nvidia.com>
…ng macro are defined Move '_with_extra_queue' and 'with_extra_queue_with_inactive_port' version to the beginning. For some vendors, all versions are defined. The generic version will be called if it is defined at the beginning Signed-off-by: Stephen Sun <stephens@nvidia.com>
Signed-off-by: Stephen Sun <stephens@nvidia.com>
Signed-off-by: Stephen Sun <stephens@nvidia.com>
bingwang-ms
reviewed
Jun 6, 2022
device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_objects.j2
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https://github.com/Azure/sonic-buildimage/blob/f0f23ebac210777333ca3f6f234317f4e211ff89/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/qos.json.j2#L82 |
Yes. We would like to use 7:0 for the purpose of saving a lossy PG and buffers. |
It doesn't make sense since both cases result in the same code Signed-off-by: Stephen Sun <stephens@nvidia.com>
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/azpw run Azure.sonic-buildimage |
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/AzurePipelines run Azure.sonic-buildimage |
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Azure Pipelines successfully started running 1 pipeline(s). |
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Looks like it is failing because #11018 was cherry-picked without updating unit test |
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@neethajohn , @bingwang-ms could you please help to review and signoff? |
neethajohn
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Jun 14, 2022
device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_objects.j2
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src/sonic-config-engine/tests/sample_output/py3/qos-mellanox4600c-c64.json
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baiwei0427
reviewed
Jun 15, 2022
device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/buffers_defaults_t1.j2
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baiwei0427
approved these changes
Jun 15, 2022
neethajohn
approved these changes
Jun 17, 2022
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There should be build issues that are caused by newly introduced commits:
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- the way to enable dual ToR feature is changed - global DSCP_TO_TC_MAP Signed-off-by: Stephen Sun <stephens@nvidia.com>
keboliu
approved these changes
Jun 20, 2022
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liat-grozovik
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Jul 20, 2022
…ario (#11261) - Why I did it Support Mellanox-SN4600C-C64 as T1 switch in dual-ToR scenario This is to port #11032 and #11299 from 202012 to master. Support additional queue and PG in buffer templates, including both traditional and dynamic model Support mapping DSCP 2/6 to lossless traffic in the QoS template. Add macros to generate additional lossless PG in the dynamic model Adjust the order in which the generic/dedicated (with additional lossless queues) macros are checked and called to generate buffer tables in common template buffers_config.j2 Buffer tables are rendered via using macros. Both generic and dedicated macros are defined on our platform. Currently, the generic one is called as long as it is defined, which causes the generic one always being called on our platform. To avoid it, the dedicated macrio is checked and called first and then the generic ones. Support MAP_PFC_PRIORITY_TO_PRIORITY_GROUP on ports with additional lossless queues. On Mellanox-SN4600C-C64, buffer configuration for t1 is calculated as: 40 * 100G downlink ports with 4 lossless PGs/queues, 1 lossy PG, and 3 lossy queues 16 * 100G uplink ports with 2 lossless PGs/queues, 1 lossy PG, and 5 lossy queues Signed-off-by: Stephen Sun <stephens@nvidia.com>
yxieca
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Jul 28, 2022
…ario (#11261) - Why I did it Support Mellanox-SN4600C-C64 as T1 switch in dual-ToR scenario This is to port #11032 and #11299 from 202012 to master. Support additional queue and PG in buffer templates, including both traditional and dynamic model Support mapping DSCP 2/6 to lossless traffic in the QoS template. Add macros to generate additional lossless PG in the dynamic model Adjust the order in which the generic/dedicated (with additional lossless queues) macros are checked and called to generate buffer tables in common template buffers_config.j2 Buffer tables are rendered via using macros. Both generic and dedicated macros are defined on our platform. Currently, the generic one is called as long as it is defined, which causes the generic one always being called on our platform. To avoid it, the dedicated macrio is checked and called first and then the generic ones. Support MAP_PFC_PRIORITY_TO_PRIORITY_GROUP on ports with additional lossless queues. On Mellanox-SN4600C-C64, buffer configuration for t1 is calculated as: 40 * 100G downlink ports with 4 lossless PGs/queues, 1 lossy PG, and 3 lossy queues 16 * 100G uplink ports with 2 lossless PGs/queues, 1 lossy PG, and 5 lossy queues Signed-off-by: Stephen Sun <stephens@nvidia.com>
skbarista
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that referenced
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Aug 17, 2022
…ario (sonic-net#11261) - Why I did it Support Mellanox-SN4600C-C64 as T1 switch in dual-ToR scenario This is to port sonic-net#11032 and sonic-net#11299 from 202012 to master. Support additional queue and PG in buffer templates, including both traditional and dynamic model Support mapping DSCP 2/6 to lossless traffic in the QoS template. Add macros to generate additional lossless PG in the dynamic model Adjust the order in which the generic/dedicated (with additional lossless queues) macros are checked and called to generate buffer tables in common template buffers_config.j2 Buffer tables are rendered via using macros. Both generic and dedicated macros are defined on our platform. Currently, the generic one is called as long as it is defined, which causes the generic one always being called on our platform. To avoid it, the dedicated macrio is checked and called first and then the generic ones. Support MAP_PFC_PRIORITY_TO_PRIORITY_GROUP on ports with additional lossless queues. On Mellanox-SN4600C-C64, buffer configuration for t1 is calculated as: 40 * 100G downlink ports with 4 lossless PGs/queues, 1 lossy PG, and 3 lossy queues 16 * 100G uplink ports with 2 lossless PGs/queues, 1 lossy PG, and 5 lossy queues Signed-off-by: Stephen Sun <stephens@nvidia.com>
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Why I did it
Support Mellanox-SN4600C-C64 as T1 switch in dual-ToR scenario
buffers_config.j2On Mellanox-SN4600C-C64, buffer configuration for t1 is calculated as:
Signed-off-by: Stephen Sun stephens@nvidia.com
How I did it
How to verify it
Run regression test.
Which release branch to backport (provide reason below if selected)
Description for the changelog
Link to config_db schema for YANG module changes
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