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Add HyperRAM implementation using ECP5 DQS logic #244

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merged 2 commits into from
May 2, 2024

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@miek miek commented Apr 22, 2024

Fixes #236

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miek commented Apr 22, 2024

Hmm. I didn't realise that the older Cynthion hardware has the HyperRAM on the top-side, so the generic interface can't use the X2 primitives - this'll need a bit of a rethink.

@miek miek marked this pull request as draft April 22, 2024 10:27
This allows for use on other platforms, rather than enforcing the LunaECP5DomainGenerator
@miek miek force-pushed the hyperram_dqs branch 2 times, most recently from 9c9c56b to 1f19390 Compare April 29, 2024 23:35
@miek miek marked this pull request as ready for review April 30, 2024 10:51
@miek miek changed the title Convert HyperRAM interface to 32-bit width (4:1) and add implementation using ECP5 DQS logic Add HyperRAM implementation using ECP5 DQS logic Apr 30, 2024
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miek commented Apr 30, 2024

For now I've reverted the changes to the previous implementation, and just added the new 32-bit wide 4:1 DQS-based implementation.

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Great work! I left some suggestions in the comments.

luna/gateware/interface/psram.py Outdated Show resolved Hide resolved
luna/gateware/interface/psram.py Outdated Show resolved Hide resolved
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miek commented May 2, 2024

Thanks! I've made the suggested changes.

@miek miek merged commit 8378945 into greatscottgadgets:main May 2, 2024
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Add support for using ECP5 DQS logic in HyperRAM interface
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